ECE 290_ LAB #4 - Mallard ECE 290 Computer Engineering I...

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Mallard ECE 290: Computer Engineering I - Spring 2007 - ECE 290: L... https://mallard.cites.uiuc.edu/ECE290/material.cgi?SessionID=mding3_... 1 of 5 4/20/2007 4:00 AM ECE 290: LAB #4 (due Mar 5, 3 pm) LAB 4: SR Latches and Flip-Flops 1 Introduction In this lab, you will compare the behavior of the following: SR latch with control input, master-slave SR F/F, and positive-edge-triggered SR F/F. These three circuits share the same function table (Table 1) but differ significantly in the conditions under which their outputs will change. TABLE 1 S R Q Q' 0 0 no change 0 1 Q=0, Q'=1 1 0 Q=1, Q'=0 1 1 Undefined SR Function Table For this lab, create a new directory in your ece290 work directory called lab4 , and create a new library mapping to this directory in HDL Designer called LAB4. 2 Circuit Diagrams Note: Remember to print out copies of each of your finished designs to hand in. 2.1 SR Latch with Control Input Use a new block diagram in HDL Designer to enter the clocked SR latch of Figure 1 below. The moduleware library's Logic category contains all of the needed gates. Call the circuit inputs S, R, and C and the outputs Q and Qbar. Edit the title box as in previous labs.
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Mallard ECE 290: Computer Engineering I - Spring 2007 - ECE 290: L... https://mallard.cites.uiuc.edu/ECE290/material.cgi?SessionID=mding3_... 2 of 5 4/20/2007 4:00 AM Save your design in the LAB4 library as sr_latch 2.2 Master-Slave SR Flip-Flop Create a new block diagram to enter the master-slave SR F/F of Figure 3 below. Use that SR latch that you just created in your LAB4 library and the inv gate from the moduleware library's 'Logic' category. Include output ports on the Y and Ybar nets so that these signals can be displayed when you simulate.
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