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Unformatted text preview: ECE 290: LAB #8 (due April 13 at noon) ECE 290: LAB #8 (due April 13 at noon) ECE 290: LAB #8 (due April 13 at noon) ECE 290: LAB #8 (due April 13 at noon) LAB 8: CPU Design III LAB 8: CPU Design III LAB 8: CPU Design III LAB 8: CPU Design III - Control and Programming Control and Programming Control and Programming Control and Programming Introduction Introduction Introduction Introduction In this lab, we will be using the entire LC-3 architecture. First, to get you comfortable with using the LC-3 on HDLDesigner, you will debug one of the LC-3's microinstructions. For the second part, you will create a new instruction for the LC-3. Last, you will use this new instruction in a program for the LC-3. Note that this lab will take a long time. Most of the second and third parts of this lab are to be completed on paper before you check your designs with the simulator. Note that the EWS labs are usually crowded at the end of the semester, so don't wait until the last minute to do the simulation parts. Remember that there is an EWS lab in the basement of Grainger Library in addition to the one in DCL. Create a "lab8" directory in your EWS work area. For this lab, you will need to download the library that contains the LC-3 architecture. The file can be found at http://courses.ece.uiuc.edu/ece290/Tools/lab8_webpage.html , named "LAB8.tar.gz". Save this file in your lab8 directory, and unpack it using the gunzip LAB8.tar.gz and tar -xf LAB8.tar commands. Create a library mapping to this directory in HDLDesigner. Be sure that the library name is "LAB8" and that the root is the "lab8" directory that you saved the library in. The link to the LC-3 appendicies, from Lab 7, is copied here: (there are underscore characters in the html file name, not spaces): http://highered.mcgraw-hill.com/sites/0072467509/student_view0/appendices_a__b__c__d____e.html For reference, the table of control signal values from Lab 7 is duplicated here. Table 1 Table 1 Table 1 Table 1: LC-3 Datapath Control Signal Binary Descriptions Signal Signal Signal Signal Description Description Description Description Signal Signal Signal Signal Description Description Description Description LD.MAR =1, MAR is loaded GateMARMUX =1, MARMUX output is put onto system bus LD.MDR =1, MDR is loaded GateMDR =1, MDR contents are put onto system bus LD.IR =1, IR is loaded GateALU =1, ALU output is put onto system bus LD.PC =1, PC is loaded GatePC =1, PC contents are put onto system bus LD.REG =1, Reg. File is loaded LD.CC =1, updates status bits from system bus MIO.EN =1, Enables memory, chooses memory output for MDR input =0, Disables memory, chooses system bus Page 1 of 12 Mallard ECE 290: Computer Engineering I - Spring 2007 - ECE 290: LAB #8 (due April ......
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- Spring '08
- Central processing unit, Mallard ECE