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21 - 28-Jun-11—1:44 PMPLDs CPLDs1University of Florida...

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Unformatted text preview: 28-Jun-11—1:44 PMPLDs, CPLDs1University of Florida, EEL 3701 – File 21© Drs. Eric M. SchwartzEEL 3701EEL 3701Menu• Programmable Logic Devices (PLDs)>Programmable Array Logic (PALs)Look into my ...>Programmable Logic Arrays (PLAs)• PAL/GAL 16V8• CPLD: Altera’s MAX 7064 and MAX 3064• Read Roth: Sections 9.6-9.8(Sections 16.4-16.6)1University of Florida, EEL 3701 – File 21© Dr. Eric M. SchwartzSee examples on web:Lam Ch 6 PLD figs, PAL/GAL info, m7000.pdf, m3000a.pdf, (specs on MAX 7064, 3064)• (Optional) Read Lam: Sections 6.4EEL 3701EEL 3701Programmable Logic Devices and Programmable Logic Arrays (PLA’s)• In conventional MSOP design, a function of 10 inputs and 8 See Lam Section 6.4outputs can be expressed as: > Zi= f (x, x1, ... , x9), i = 0, 1, ... , 7 XX1X2X3 XZZ1Z2Z......2University of Florida, EEL 3701 – File 21© Dr. Eric M. SchwartzX4X5X6X7X8X9Z3 Z4Z5Z6Z7Xi’sZi.........28-Jun-11—1:44 PMPLDs, CPLDs2University of Florida, EEL 3701 – File 21© Drs. Eric M. SchwartzEEL 3701EEL 3701PLD Shorthand NotationLAM Fig 6.93University of Florida, EEL 3701 – File 21© Dr. Eric M. SchwartzEEL 3701EEL 3701PLAPLAPLAExample Simplified Schematics4University of Florida, EEL 3701 – File 21© Dr. Eric M. SchwartzLAM Fig 6.1028-Jun-11—1:44 PMPLDs, CPLDs3University of Florida, EEL 3701 – File 21© Drs. Eric M. SchwartzEEL 3701EEL 3701Simplified Schematics5University of Florida, EEL 3701 – File 21© Dr. Eric M. SchwartzLAM Fig 6.11PLAEEL 3701EEL 3701Programmable Logic Devices and Programmable Logic Arrays (PLA’s)Q: Any problems with MSOPs? Any problems with MSOPs?...
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  • Spring '08
  • LAM
  • Logic gate, Programmable logic device, Programmable logic array, Programmable Array Logic, Dr. Eric M. Schwartz, Eric M. Schwartz

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21 - 28-Jun-11—1:44 PMPLDs CPLDs1University of Florida...

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