24 - GCPU, Comp Org, 68HC11, Assembly 28-Jun-111:46 PM EEL...

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28-Jun-11—1:46 PM GCPU, Comp Org, 68HC11, Assembly 1 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo EEL 3701 EEL 3701 Menu • Computer Organization •Programming Model for the an example microprocessors (the G-CPU & Motorola 68HC11) • Assembly Programming Look into my . .. 1 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo See examples on web: DirAddr.asm, ExtAddr.asm, IndAddr.asm, ImmAddr.asm, Phone.asm EEL 3701 EEL 3701 Computer Functional Block Diagram MEMORY I/O ALU 2 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo DATA CONTROL CONTROL CPU
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28-Jun-11—1:46 PM GCPU, Comp Org, 68HC11, Assembly 2 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo EEL 3701 EEL 3701 Memory and I/O Units MU i CONTROL MEMORY I/O CPU ALU Memory Unit Data Address MEMORY UNIT Data Out Read/Write Enable Data In Status 3 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo I/O Unit INPUT/OUTPUT UNIT Device Address Control Data Out Data In Status Device Identity EEL 3701 EEL 3701 Control Unit Control Unit Program Counter • Functions Instruction Register Instruction Decoder SDR SAR storage data (buffer) reg storage address reg > Decodes Instruction > Generates Control Signals > Generates Timing Signals • Hardware > Instruction Register (IR) >Program Counter (PC) 4 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo Control Sequence Generator Clock ALU Misc. Misc. > Control Signal Generator >Clock Status Register
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28-Jun-11—1:46 PM GCPU, Comp Org, 68HC11, Assembly 3 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo EEL 3701 EEL 3701 Arithmetic/Logic Unit (ALU) Arithmetic/Logical Unit (ALU) Ft i Shift/No Shift Left/Right Logical/Arithmetic from C.U. • Functions > Arithmetic operations on data > Logical operations on data > Shifting operations on data > Status checking on results • Hardware Shifter Status Register Function Code (from Control Unit) Flags to Control Unit ALU 5 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo > Arithmetic/Logical circuits > Accumulator >Shifter > Status Register Accumulator To Memory Control Unit) From Memory EEL 3701 EEL 3701 Instruction Register • The n-bit instruction register consists of a MUX and a D FF and a D-FF. >The MUX has a select line, IR_LD >The output of the MUX goes to the D input of the D-FF >The output of the D-FF is the 0 input of the MUX >The 1 input of the MUX comes from the input bus 6 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo
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28-Jun-11—1:46 PM GCPU, Comp Org, 68HC11, Assembly 4 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo EEL 3701 EEL 3701 Programming Model for GCPU 8-bit Accumulators A And B A 0 7 B 0 7 Index (Displacement) Register X Index (Displacement) Register Y Memory Address Register ( Hidden ) MAR Program Counter PC 0 1 IX 0 15 IY 0 15 MAR 0 15 PC 0 15 7 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo Zero Negative N Z Condition Code Register (CCR) IR 0 5 Instruction Register ( Hidden ) IR EEL 3701 EEL 3701 Programming Model for Motorola 68HC11 0 7 0 7 A B D0 15 8-BIT ACCUMULATORS A AND B OR STACK SP 9 SP AFTER I.R.
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24 - GCPU, Comp Org, 68HC11, Assembly 28-Jun-111:46 PM EEL...

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