EEL3701Ex1F07Solution

EEL3701Ex1F07Solution - University of Florida EEL...

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Unformatted text preview: University of Florida EEL 3701—Fall 2007 Drs.‘Lam, Schwartz and Arroyo Department of Electrical & Computer Engineering Wednesday, 3 October 2007 k Page 1/12 Exam 1 A Last Name, First Name Instructions: 0 Turn ofi’ all cell ghones, beepers and other noise making devices. 0 Show all work on the (front of the test papers. Egg each answer. If you need more room, make a clearly indicated note on the front of the page, ’MORE ON BACK ”, and use the back. The back of the page will hit be graded without an indication on the fiont. You may m use any notes, HW, labs, other books, or calculators. This exam counts for 24% of your total grade. Read each question carefully and [allow the instructions. You must pledge and sign this page in order for a grade to be assigned Put your name at the top of this test page and be sure your exam consists of 1_2_ distinct pages. Sign your name and add the date below. > V The point values for problems may be changed at prof ’s discretion Good luck & GO Gators/f Notation reminder: A(H) is the same as A.H.. For each circuit design, equations must n_0_t be used as replacements for circuit elements. For each mixed—logic circuit diagram, label inputs/outputs of each gate with the appropriate logic equations. Boolean expression answers must be in lexical order,( i. e., /A before A, A before B, & D3 before D2). Label the inputs and outputs of each circuit with activation-levels. For K—maps, label each grouping with the appropriate equation. PLEDGE: On my honor as a University of Florida student, I certify that I have neither given nor received any aid on this examination, nor I have seen anyone else do so. Good Evening! Welcome! l x 3 SIGN YOUR NAME DATE (3 Oct 2007) Regrade comments below: Give page # and problem # and reason for the petition. ‘ University of Florida EEL 3701—Fa112007 Drs. Lam, Schwartz and Arroyo Depaflment of Electrical & Computer Engineering Wednesday, 3 October 2007 Page 2/12 Exam 1 Last Name, First Name [6%] 1. Do the following arithmetic problems. Remember to show ALL work here and in EVERY problem on this exam. (2%) a) Determine the unsigned binary, octal, hexadecimal, and BCD representations of the number 17010. 21/13 Binary; / & m m d Octal: Z /O Hex: 5 {L225 / BCD: afibllflfi/(fldfld ~2— Li" 2 Lé/ 2. L1. 0 a / (2%) b) Determine the 8-bit signed magnitude, 1’s complement, and 2’s complement representations of the decimal number -8510. EM SignedMagzgz /€/§/0/ % / u l’sComp: 4 04 as /&/ fl 5/: /§/& 2,5C0mp: /(7/(2 /&/ / %z 5% &/flffl/&/ (2%) c) What is 17010 -8510 in 8—bit 2’s complement? Remember that you must show a_ll work. (17010-851o)2: d/0/ ______,4_.___ /‘7& /&/Q/a/0 7‘ (~55) /z7/&A/&// 74 3'5 ’ bay/1‘9 M/ is E 5. j. l University of Florida EEL 3701——Fall 2007 Drs. Lam, Schwartz and Arroyo Department of Electrical & Computer Engineering Wednesday, 3 October 2007 Page 3/12 Exam 1 Last Name, First Name [10%] 2. Answer the following questions given the below truth table with inputs A, B and C and output f. (2%) a) Write the corresponding minterm (i.e., canonical sum of products CSOP) —g_1_'— maxterm (i.e., canonical product of sums CPOS) In equation for f (one or the other, but not both). ('6; a?) M: (2m »Mrg+c)»(4r’rc ewe/c7 Which did you write above? (circle one): Minterms (CSOP) Maxterm (CPOS) (1%) b) Completely fill in the K-map (to the right) with 1’s and 0’s (no blanks). (2%) c) With the K-map to the right, find the minimum sum of products (MSOP) solution. (Label each grouping with the appropriate expression and then write the total equation. Use proper lexical ordering; i.e., /A before A, A before B, & D3 before D2.) fMSOP I a’ Z 7% 7‘ flic (3%) d) Completely fill in the K-map (to the right) with 1’s and 0’s (no blanks) and find the minimum. product of sums (MPOS) solution. Note: The order of the signals in the K-map has been changes! (BC is on top) MOS: 75745 #7425 (,7 f5) ' w...# M,“ (1%) 6) Are stQp and fMpQS equivalent expressions? Why? Circle One: ) No not equivalent) . ' ~ ,/ r , ’ . W Xefz 21% v. M n A, (1%) t) Which soluns is less costl gates) and why? Circle One: MSOP MPOS flora: 3/44/95 3M7"; / fix? W 3 EEL 3701—Fa112007 Wednesday, 3 October 2007 Exam 1 University of Florida Department of Electrical & Computer Engineering Page 4/12 Drs. Lam, Schwartz and Arroyo Last Name, First Name [10%] 3. Using any technique you desire, simplify the following equation. Give the result as a minimum sum of products (MSOP). Show all work! Z=/A(B+C)+/A/C+/A/B(/D+/CD) 2: M +fic+ fig» ZE5+ ZZZ? f a/ m 00 0&0 6990/ %ASOP = .fi—_—_—______v EEL 3701—Fa112007 Wednesday, 3 October 2007 Exam 1 University of Florida Department of Electrical & Computer Engineering Page 5/12 Drs. Lam, Schwartz and Arroyo Last Name, First Name [9%] 4. Logic vs. voltage using adders. A 4-bit adder will add two 4-bit numbers: A3A2A1A0 and B3B2B1Bo; and produce a 4-bit sum 83828180 and a carry—out C4. For example: If A3A2A1A0 = B3B2B1B0 : Then 83828180 = 0101, with C4 =1 The above example is to help you review how the adder works. It is n_ot a part of the test. The following 4-bit adder has signals A3, B3, A2, B2, 8;, and S0 and C4 assigned to active low. All other signals are assigned active high. 0/ @0./! HH H L H H A2 C4 0 Cout Cin (a) We applied the above VOLTAGE values to add two binary numbers. What two binary numbers are we trying to add? A3=_<9_.(00r1) A2=_0(oor1) A1=_/(00r1) Ao=0‘(00r1) B3=L(Oor1) BZ=Q‘(Oor1) Bl=_/:(00r1) Bo=_/_(00r1) / / fi / (b) What VOLTAGE values (i.e., high H or low L) do you expect for 83828180 and C4? @ o s3=fi(HorL) sz=fi(HorL) sl=fl(HorL) So=£(HorL) C4=i(HorL) University of Florida EEL 3701—Fall 2007 Drs. Lam, Schwartz and Arroyo Department of Electrical & Computer Engineering Wednesday, 3 October 2007 Page 6/12 Exam 1 i Last Name, First Name 5 [7%] 5. Determine the equation directly implemented with this mixed-logic circuit. Do n_ot : minimize the equation. It is 291 necessary to put the equation in lexical order. For partial credit, label the intermediate signals from each gate. ‘ [10%] 6. Directly implement the below equation with a mixed-logic circuit » diagram. Use only gates available on 74’02 chips. (Use the appropriate mixed-logic symbols). Label all gates and pi_n numbers as you should be doing in lab. Pick Whatever activation levels you want for the inputs, but make the output W active—low. W=(G*/A*T)+(/O*R*/S) G([.) i ‘OZA 02,1 92% A(//) - ‘, l_ Y E T(4)_ 0(fl)_ EEL 3701—Fa112007 Wednesday, 3 October 2007 Exam 1 University of Florida Department of Electrical & Computer Engineering Page 7/12 [12%] 7. Create an equivalent 8-input multiplexer using 4-input multiplexers (see truth table), and using the minimum number of components. You can use additional gates if necessary. However, each gate counts as a component. A 4-input MUX also counts as one component. Drs. Lam, Schwartz and Arroyo Last Name, First Name University of Florida Department of Electrical & Computer Engineering Page 8/12 BEL 3701—Fa112007 Wednesday, 3 October 2007 Exam 1 [12%] 8. Implementation of Logic with Decoders Last Name, Drs. Lam, Schwartz and Arroyo First Name Given the following 2 logic equations and activation levels for the signals, implement them with the following decoder and any number of 3—input OR gates (ONLY). @@ ZZ B.H C.H " For partial credit, show work here: For maximum credit, use the minimum number of gates. Just draw the gates. You don’t have to label them (e.g., like 7411) Note the * is the AND operator and IA is “NOT A”. AI ' active high, except ZZ which is active low. Z1 = /A*/B*/C + A*/B*C + 0 / 0 / /A*E ““ 0/ O University of Florida EEL 3701—Fall 2007 Drs. Lam, Schwartz and Arroyo Department of Electrical & Computer Engineering Wednesday, 3 October 2007 Page 9/12 Exam 1 Last Name, First Name [8%] 9. Given the following simple circuit consisting of two NAND gates, derive the next state voltage table (use L and H) for the device. In other words, given each combination of voltage values for A, B, and X, What are the values for X and Y after the circuit becomes stable? (a) i 3“ [8%] EEL 3701—Fa112007 Wednesday, 3 October 2007 Exam 1 University of Florida Department of Electrical & Computer Engineering Page 1.0/12 Drs. Lam, Schwartz and Arroyo Last Name, 10. Synchronous component (flip-flop) vs. combinatorial component (MUX) ZI(H) JrHr——— J K( CLK 2-to-1MUX 22(H) D(H SEL(H) Given the above circuit, complete the following voltage timing diagrams: First Name Show propagational delays and go as far as you can. 10 University of Florida EEL 3701—F all 2007 Drs. Lam, Schwartz and Arroyo Department of Electrical & Computer Engineering Wednesday, 3 October 2007 Page 11/12 Exam 1 Last Name, First Name [8%] 11. Building switches and LEDs [4%] (a) Shown below are two switches X1 and X2. Complete the design of the two switches to generate two input signals: active low X1.L and active high X2.H. In other words, make the connections among the switches, resistors, VCC, and GND to produce the two signals. . [2%] (b) Coming out of the digital circuit are two output signals. Make the connections among the LED’s, resistors, VCC, and GND to display the active low output 21 .L to an active low LED and the active high output 22H to an active high LED. An LED should be lit when the corresponding output is “true”. [2%] (c) The TA wants to see LEDs on the input signals. Make the connections among the LED’S, ? resistors, VCC, and GND to display the active low input X1.L to an active low LED and the active high input X2.H to an active high LED. An LED should be lit when the corresponding input is “true”. Kata/3% 5MB «15V Switch Switch X1 X2 Outputs 1 Z1.L Digital Circuit +§V , . YZfl M ll University of Florida EEL 3701—Fall 2007 Drs. Lam, Schwartz and Arroyo Department of Electrical & Computer Engineering Wednesday, 3 October 2007 Page 12/12 Exam 1 Last Name, First Name 1 Laws and Theorems of Boolean Algebra Operations With 0 and 1: 1.X+0=X 1D.X-1=X 2.X+l=l 2D.X00=0 Idempotent laws: 3.X+X=X 3D.X°X=X Involution laws: g ' 4. (X’)’ = X Laws of complementarity: 5.X+X’=1 5D.X-X’=0 Commutative laws: 3 6. X +Y = Y + X 6D. XY=YX Associative laws: 7. (X+Y)+Z=X+(Y+Z)=X+Y+Z 7D. (XY)Z=X(YZ)=XYZ Distributive laws: I 8. X(Y + Z) =XY + XZ 8D. X + Y2 = (X +Y)(X + Z) Simplification theorems: 9. XY+XY’=X 9D. (X+Y)(X+Y’)=X 10.X+XY=X 10D.X(X+Y)=X 11. (X+Y’)Y=XY 11D. XY’+Y=X+Y DeMorgan’s laws: 12. (X+Y+Z+...)’=X’Y’Z’ 12D. (XYZ...)’=X’+Y’+Z’ 13. [f(A, B, ..., Z, 0,1, +, ')]’ = f(A’, B’, ..., Z’, 1, 0, -, +) Duality: 14. (X+Y+Z+...)D=XYZ... 14D. (XYZ...)D=X+Y+Z+... 15. [f(A,B, 0, 1,+,-)]D=f<A,B, 1,0,-,+) Theorems for multiplying out and factoring: 16. (X + Y)(X’ + Z) = XZ + X’Y 16D. XY + X’Z = (X +Z)(X’ +Y) Consensus theorems: 17. XY +YZ +X’Z = XY +X’Z 17D. (X + Y)(Y + Z)(X’ + Z) = (X + Y)(X’ +2) 1 2 ‘ ...
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This note was uploaded on 07/08/2011 for the course EEL 3701 taught by Professor Lam during the Spring '08 term at University of Florida.

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EEL3701Ex1F07Solution - University of Florida EEL...

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