University of Florida
EEL 3701 — Summer 2011
Dr. Eric M. Schwartz
Department of Electrical & Computer Engineering
LAB 6: Arithmetic Logic Unit (Element of a CPU)
The objective of this lab is to design and augment a simple
arithmetic logic unit (ALU) with registers and several
multiplexers to create a simple central procession unit (CPU).
This device will perform simple addition, logical
complement, logical AND, logical OR and shifting of 4-bit
Prototype Board, Wires, Switches, LEDs and UF-3701
Useful Quartus Components:
In “others | maxplus2” library
74153: Two 4-input MUX’s (recommended)
74151: 8-input MUX (recommended)
74283: 4-bit Adder (recommended)
7474: Dual D-FF (not recommended)
74175: Quad D-FF (not recommended)
In “megafunctions | gates” library
mux (not recommended)
lpm_mux (not recommended)
In “primitives | storage” library
In “primitives | logic” library
not, and2, or2, bor2, etc.
In “primitives | pin” library
In “primitives | other” library
A block diagram of the CPU you will design is shown in
The device has one 4-bit wide INPUT bus and one 4-bit
wide OUTPUT bus.
These buses are used to bring data
to and from the ALU.
The OUTPUT bus is fed back for
possible re-entry to the system.
REG A and REG B are 4-bit wide registers (i.e., 4 D
Flip-Flops) that are used to hold data originating from
MUX A and MUX B.
MUX A & B (each containing
four 4-input multiplexers) are used to connect a
particular bus to REG A and REG B.
A bus is connected
as described in Table 1.
The outputs of REGA and REGB are thus fed back to
MUX A and MUX B inputs as well as to a combinatorial
logic block. The signals REGA and REGB are system
The combinatorial logic block is used to perform data
complement, addition, ORing, ANDing, and shifts.
MUX C consists of four 8-input multiplexers.
used to select a particular operation for outputs.
three select lines MSC2:0 function as shown in Table 2
(where the most significant bit is on the left).
The carry output, Cout, should come directly from the
adder circuit (with no additional circuit necessary).
COMPILATION AND SIMULATION
In this lab, your signals REGA and REGB are required
outputs of the circuit, since these are the actual system
It is often helpful to create extra output signals (as
discussed below, called
) so that your circuit
design is easier to debug (in simulation and in hardware).
For example, you might want to output the signals that come