Lam_119_to_122 - FROBLEMS " 119 BCD adder Figure...

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Unformatted text preview: FROBLEMS " 119 BCD adder Figure 4.25 BCD adder for Problem 4.5. 4.6. Using 75’85 comparators, design a 16-bit magnitude comparator. 4.7. Design the 4-bit magnitude comparator of Fig. 4.26, using a 74’85 comparator plus any additional gates that are needed. Note that this comparator has three more than the usual number of outputs. These are <=, > = , and <>, which represent less than or equal to. greater than or equal to, and not equal to. respectively. Comparator A3-Ao (A) B) (A > = B) 8-3 3 o {A=B) (A > B).IN (A < = B) (A = BHN (A < B) (A < BMN {A <> B) Figure 4.26 Comparator for Problem 4.7. 4.8. Design a 5-to-32 decoder using 74’138 decoders and any additional gates that are required. 4.9. Given an 8-bit address A7—Ao, what are the addresses that will enable the modules M0, Ml, M2, and M3 shown in Fig. 4.27. For convenience, use X for a don’t-care address bit. 2-to-4 decoder Figure 4.27 Circuit for Probiem 4.9. 4.10. Using the truth table for a BCD-tofI-segment decoder shown in Fig. 4.ll(c), derive the logic equations for the seven outputs a, b. c, d, e, f, and g. 120 4/COMBINATIONAL MSI CIRCUIT ELEMENTS 4.11. A chain of 74'47 BCD-to—7-segment decoders can be connected together as shown in Fig. 4.12(c) to display leading zeros as blanks. Reconnect the 74'473 in such a way that leading zeros are displayed as zeros. 4.12. Design Module M in Fig. 4.28 to obtain a l6—to-4 priority encoder. (Hint: Module M is a combinational circuit with eight inputs and five outputs. You are to determine the logic equations for the five outputs.) 1640-4 priority encoder Figure 4.28 Encoder for Problem 4.12. 4.13. The enable output E0 and enable input E! of a 74'148 can be used to cascade 74'148 priority encoders for easy octal expansion. Such an expansion for the 74’1485 of Fig. 4. 29(a) is shown in Fig. 4.29(b). Show connections for the 74’1485 of Fig. 4.29{a) that will accomplish this expansion. No additional gates are required. (a) PROBLEMS -1 21 EI A0 Al A3 A3 A. A5 A6 A. BO 3. 131 B3 B4 BS 13.6 3. z2 z1 z0 v2 v1 v0 (332 GSYEO 0 X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 l 0 0 0 0 0 0 0 0 0 0 0 0 0 0 O 0 0 0 0 0 O O 0 0 i l l 0 0 0 O 0 0 0 0 0 0 0 0 0 0 D 0 0 0 0 0 O 0 l 0 l X 1 0 0 0 0 0 0 O 0 0 0 O 0 O 0' 0 0 0 0 0 l O 1 0 l X X l 0 0 0 0 0 0 0 0 0 O 0 0 0 D 0 O 0 1 O 0 l 0 l X X X l 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 l l 0 l 0 l X X X X l 0 0 0 0 0 0 0 0 0 0 0 0 O 0 l 0 0 0 l 0 l X X X X X l 0 O 0 0 0 0 0 0 0 0 0 0 0 i 0 l O l 0 l X X X X X X l 0 0 0 0 0 0 0 0 0 0 0 0 i l 0 0 l 0 1 X X X X X X X l 0 0 0 0 0 0 0 0 0 0 0 l l 1 O l 0 l X X X X X X X X l 0 0 0 O 0 0 0 0 0 0 O 0 0 l 0 0 1 X X X X X X X X X l 0 0 0 0 0 0 0 0 l 0 0 0 l 0 0 l X X X X X X X X X X l 0 0 0 0 0 0 l O 0 0 0 1 O 0 l X X X X X X X X X X X l 0 0 0 0 0 l 1 0 0 0 l 0 0 l X X X X X X X X X X X X I 0 0 0 1 0 QC 0 0 l 0 0 1 X X X X X X X X X X X X X l 0 0 l 0 l O 0 0 l 0 0 i X X X X X X X X X X X X X X1 0 l l O 0 0 0 l 0 0 l X X X X X X X X X X X X X X X1 l l I 0 O O l 0 O (b) Figure 4.29 Table and components for Problem 4. l3. 4.14. (a) Determine the complete truth table for the four-input MUX shown in Fig. 4.16. (b) Derive the logic equation for Z. 4.15. In Fig. 4.20. a lfi-input MUX is realized with 4 four-input MUXs and a decoder. But, suppose no decoder is available. Design a [IS-input MUX using any number of 4—input MUXs (74'253), but no decoders. 4.16. Using a 74‘148 priority encoder and any additional gates that are required. design the circuit of Fig. 4.30 for generating the S0 and S1 control inputs for the circuit of Fig. 4.18. Each of the requesting devices (A. B. C. and D) can request a connection to device X through the signals REQA, REQB. REQC, and REQD, respectively. If there are competing requests. then the order of priority is as follows: D, C, B, and A, with D having the highest priority. If no request is made, then device X is connected to A by default. CONTR SIJ-l SO.H Figure 4.30 Circuit for Problem 4.16- 4.17. Design the circuit BIDIR of Fig. 4.31 such that the signal DATA is bidirectional. Specif- ically. when IOCT R is l (H), then DATA is connected to INPUT and the direction of the data flow is “in.” But when IOCTR is 0 (L). then DATA is connected to OUTPUT and the direction of the data flow is “out.” (Hint: Use 74’ 125 three-state logic elements.) 122 4/COMBINATIONAL MSI CIRCUIT ELEMENTS BIDIR DATAH INPUT-H lOCTR.H OUTPUTJ-l Figure 4.31 Circuit for Problem 4.17. 4.18. (3) Discuss the similarities and the differences between a decoder and a demultiplexer. (b) An encoder performs the inverse function of a decoder, and a multiplexer performs the inverse function of a demultiplexer. Then. is there any relationship between an encoder and a multiplexer? Explain. 4.19. What is the maximum number of standard-TIL inputs that an‘ALSéTI'L output can drive? 4.20. If the signal MEMCS shown in Fig. 4.32 activates the CS inputs of a bank of memory chips with the specified characteristics, how many CS inputs can it safely drive? 1km Memory chip: Vm.I = 2.4 V min 741.502 1“, = ‘40 “A max MEMCSJ. 1m = 40 M max 10L = 16 mA max lo“ = -1 mA max Figure 4.32 Circuit for Problem 4.20. 4.21. What is the noise margin for the ALS-TTL series components? 4.22. If an ALS-TI‘L output drives a number of LS-TTL inputs, what is the resultant noise margin? 4.23. Given the Exclusive OR gate of Fig. 4.33(a), complete the shown timing diagram for Z in Fig. 4.33(b). Be sure to show and label the propagation delays tPHL and tPLH. B.H A.H 2.1-! (a) (b) Figure 4.33 Gate and timing diagram for Problem 4.23. 4.24. Given the circuit diaggm of Fig. 434(3), complete the shown timing diagram in Fig. 4.34(b) for the signals A and Z. Be sure to show and label the propagation delays IPHL and IPLH. 7 RH A.H l I in (a) 21-! (b) Figure 4.34 Gate and timing diagram for Problem 4.24. ...
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Lam_119_to_122 - FROBLEMS &amp;quot; 119 BCD adder Figure...

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