4 - 1. When a timer is configured in the Gated Operation...

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1. When a timer is configured in the Gated Operation Mode, why do we have to be concerned about the timing characteristics of TxCK? What are the timing requirements T2CK has to meet when it’s used for Gated Mode? (10 points) Because there is setup time and hold time for all electronic devices, and the MCU needs time to response for the signal sent in in TxCK and let the timing begin, it is necessary for us to consider the timing characteristics. If the high level time is not big enough, it is impossible for us to measure the period of it. What’s more, the resolution will be affected, too. Also the rising edge and falling edge are needed, as well. The time should not be too long, too, since it should not pass the limitation of the register size if the software will not assist in timing. Also the time should not be forever, otherwise the software can not hold that number. When Vdd<2.7 v. The high level signal should be larger than (12.5 NS OR 1 TPB) +25 NS. And the time between two high level signal time should be larger than greater of [(25ns or 2
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This document was uploaded on 06/24/2011.

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4 - 1. When a timer is configured in the Gated Operation...

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