16 - 24-Mar-11-10:33 AM Main Timer System, RTI, TOI 68HC12...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
24-Mar-11—10:33 AM Main Timer System, RTI, TOI 68HC12 & TI DSP 1 University of Florida, EEL 4744 – File 16 © Drs. Schwartz & Arroyo EEL 4744 EEL 4744 Menu • Main Timer System • Real-Time Interrupt (RTI) > RTI Hardware Look into my . .. > Internal Registers for RTI – RTICTL, RTIFLG • RTI Programming Examples > Using RTI interrupt > Using RTIF and polling • Free-running Counter and See docs/examples on web-site: Ti l SPRUFB0D 1 University of Florida, EEL 4744 – File 16 © Drs. Schwartz & Arroyo Timer Overflow (TOF) > Internal Registers for TOF – TCNT, TSCR , TMSK2, TFLG2 > Example using TOF Timer_example, SPRUFB0D, S&HE (Ch 10), M68HC12B/D.pdf (Sec 10,12), RTIa*.asm, RTIb.asm, CoPrRTI.asm, TimeOver.asm, TimeOver_debug.asm EEL 4744 EEL 4744 F28335 Timers (Three 32-bit) • There are three 32-bit timers, CPU-TIMER0, 1, and 2 > The 32-bit counter register TIMH:TIM is loaded with the value in the period register PRDH:PRD . The counter decrements once every (TPR[TDDRH:TDDR]+1) SYSCLKOUT cycles where every (TPR[TDDRH:TDDR]+1) SYSCLKOUT cycles where TDDRH:TDDR is the timer divider. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. SPRUFB0D 2 University of Florida, EEL 4744 – File 16 © Drs. Schwartz & Arroyo SPRUFB0D Figure 31
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
24-Mar-11—10:33 AM Main Timer System, RTI, TOI 68HC12 & TI DSP 2 University of Florida, EEL 4744 – File 16 © Drs. Schwartz & Arroyo EEL 4744 EEL 4744 F28335 Timers (Three 32-bit) • Time between interrupts, T I = T SYSCLK * (M+1) * (N+1) > If M = 3 and N = 0xF FFFF > Then T I = T SYSCLK * (3+1) * (0xF FFFF+1) f SYSCLK =7.5 MHz T SYSCLK =13.3 s = T SYSCLK * 4 * (0x10 0000) = T SYSCLK * 4 * 16 5 = 0.559 s SPRUFB0D M N 3 University of Florida, EEL 4744 – File 16 © Drs. Schwartz & Arroyo SPRUFB0D Figure 31 M+1 N+1 delays EEL 4744 EEL 4744 F28335 Timers (Three 32-bit) • Time between interrupts, T I = T SYSCLK * (M+1) * (N+1) > Find maximum T I >T I = T SYSCLK * (0xFFFF+1) * (0xFFFF FFFF+1) f SYSCLK =7.5 MHz T SYSCLK =13.3 s = T SYSCLK * (0x1 0000) * (0x1 0000 0000) = T SYSCLK * (0x1 0000 0000 0000) = T SYSCLK * 16 12 = 37.5 * 10 6 s SPRUFB0D M N 4 University of Florida, EEL 4744 – File 16 © Drs. Schwartz & Arroyo SPRUFB0D Figure 31 M+1 N+1 delays
Background image of page 2
24-Mar-11—10:33 AM Main Timer System, RTI, TOI 68HC12 & TI DSP 3 University of Florida, EEL 4744 – File 16 © Drs. Schwartz & Arroyo EEL 4744 EEL 4744 Timer Interrupt Signals SPRUFB0D Figure 32 5 University of Florida, EEL 4744 – File 16 © Drs. Schwartz & Arroyo • The timer registers are connected to the memory bus of the C28x processor • The timing of the timers is synchronized to SYSCLKOUT of the processor clock EEL 4744 EEL 4744 Timer1 Example • Run the example (timer_ex1) on the examples web page page.
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 4
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 14

16 - 24-Mar-11-10:33 AM Main Timer System, RTI, TOI 68HC12...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online