17 - 4-Apr-11-3:13 PM OC, PWM for 68HC12 & TI DSP EEL 4744...

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4-Apr-11—3:13 PM OC, PWM for 68HC12 & TI DSP 1 University of Florida, EEL 4744 – File 17 © Drs. Schwartz, Arroyo EEL 4744 EEL 4744 Menu • Introduction to OCx Output Compar • Output Compare >Output Compare: OC0 - OC7 –OM:OL >PWM example >OC7 >Forced Output Compares Look into my . .. 1 University of Florida, EEL 4744 – File 17 © Drs. Schwartz & Arroyo >Periodic Signal Generation Example See docs/examples on web-site: SPRUG04A, SPRS439H (sec 4.3), OC2PWM.asm, OC2PWM_sim_debug.asm, OC7PWM.asm, OC5SigGn.asm EEL 4744 EEL 4744 68HC12 Timer Timer System Block Diagram: OC 2 University of Florida, EEL 4744 – File 17 © Drs. Schwartz & Arroyo System S&HE: Fig 10.1 OC
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4-Apr-11—3:13 PM OC, PWM for 68HC12 & TI DSP 2 University of Florida, EEL 4744 – File 17 © Drs. Schwartz, Arroyo EEL 4744 EEL 4744 68HC12 Timer Block Diagram: OC System 3 University of Florida, EEL 4744 – File 17 © Drs. Schwartz & Arroyo Tech: Fig 12-1 EEL 4744 EEL 4744 Main Timer System S&HE: Fig 10.3 4 University of Florida, EEL 4744 – File 17 © Drs. Schwartz & Arroyo
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4-Apr-11—3:13 PM OC, PWM for 68HC12 & TI DSP 3 University of Florida, EEL 4744 – File 17 © Drs. Schwartz, Arroyo EEL 4744 EEL 4744 TIOS: Timer Input Capture/Output Compare Select Register & DDRT • TIOS - Timer Input Capture/Output Compare Select Registe IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 TIOS $0080 76543210 00000000 RESET Select Register >0 = IC; 1= OC DDRT Data Direction Register for Port T 5 University of Florida, EEL 4744 – File 17 © Drs. Schwartz & Arroyo DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 DDRT $00AF RESET • DDRT - Data Direction Register for Port T >0 = Input; 1 = Output EEL 4744 EEL 4744 TCNT and TSCR Bit 15 - - - - - - Bit 8 TCNT High $0084 0 0 0 0 0 0 0 0 RESET Bit 7 - - - - - - Bit 0 TCNT Low $0085 RESET TEN TSWA TSBCK TFFCA TSCR $008 6 University of Florida, EEL 4744 – File 17 © Drs. Schwartz & Arroyo • TEN (Timer Enable) in TSCR: >0 = disable > 1 = enable TSWAI 0 0 0 0 $0086 RESET
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4-Apr-11—3:13 PM OC, PWM for 68HC12 & TI DSP 4 University of Florida, EEL 4744 – File 17 © Drs. Schwartz, Arroyo EEL 4744 EEL 4744 Output Compare Block Diagram (from OM,OL) • Block Diagram of Output Compare (from OM,OL) S&HE: Fig 10.3 OCx Interrupt Line Free-running Counter Comparator Action Control In TCTL1 or TCTL2 OMx OLx 7 University of Florida, EEL 4744 – File 17 © Drs. Schwartz & Arroyo OCx Interrupt Enable OCx Flag FF TCx Register Pin Tech: Tab 12.1 00 Disconnect 01 Toggle 10 Reset 11 Set EEL 4744 EEL 4744 Input Capture / Output Compare Registers • TCx - Timer Input Capture / Output Compare x 76543210 Bit 15 - - - - - - Bit 8 TC0 $0090 Bit 7 - - - - - - Bit 0 $0091 Bit 15 - - - - - - Bit 8 TC1 $0092 Bit 7 - - - - - - Bit 0 $0093 8 University of Florida, EEL 4744 – File 17 © Drs. Schwartz & Arroyo Bit 15 - - - - - - Bit 8 TC7 $009E Bit 7 - - - - - - Bit 0 $009F Bit 15 - - - - - - Bit 8 TC6 $009C Bit 7 - - - - - - Bit 0 $009D RESET = $0000
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4-Apr-11—3:13 PM OC, PWM for 68HC12 & TI DSP 5 University of Florida, EEL 4744 – File 17 © Drs. Schwartz, Arroyo EEL 4744 EEL 4744 TCTL1 & TCTL2: Time Control Registers • TCTL1 & TCTL2- Timer Control Registers >Output Mode (OMx) and Output Level (OLx OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 TCTL1 $0088 76543210 00000000 RESET >Output Mode (OMx) and Output Level (OLx) 9 University of Florida, EEL 4744 – File 17 © Drs. Schwartz & Arroyo OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 TCTL2 $0089 RESET Tech: Tab 12.1 00 Disconnect 01 Toggle 10 Reset 11 Set EEL 4744 EEL 4744
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This document was uploaded on 07/11/2011.

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17 - 4-Apr-11-3:13 PM OC, PWM for 68HC12 & TI DSP EEL 4744...

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