19a - 12-Apr-11-9:34 AM SPI for 68HC12 EEL 4744 EEL 4744...

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12-Apr-11—9:34 AM SPI for 68HC12 1 University of Florida, EEL 4744 – File 19a © Dr. Eric M. Schwartz EEL 4744 EEL 4744 Menu • SPI Concepts >Problems in serial communications Look into my . .. –Timing Synchronization: How do you line up the bit boundaries? – Message Synchronization: How do you line up messages? >Synchronous data communications (SPI on HC12) solves first problem by sending clock along with message 1 University of Florida, EEL 4744 – File 19a © Dr. Eric M. Schwartz – SPI performs a “physical-level” form of serial communication >Section 11.4 in the S&HE Book Covers the SPI system See examples on web-site: SPI_Master.asm, SPI_Slave.asm, SPI_Master_Tab.asm, SPI_Out.asm EEL 4744 EEL 4744 SPI Concepts •Motorola SPI System 68HC12 68HC12 MOS MOS > SCK - Serial Clock (PS6) – Output for master – Input for slave > SS (L) - Slave Select (PS7) – Input for slave – Unrelated output for master > MOSI -Master Out/Slave In (PS5) 8 bit 8 bit Master Slave MOSI MOSI MISO MISO SCK SCK GND SS SS 2 University of Florida, EEL 4744 – File 19a © Dr. Eric M. Schwartz > MISO - Master In/Slave Out (PS4) XXXX XXXX YYYY YYYY YYYY YYYY XXXX XXXX Initial After 8 SCK’s Initial After 8 SCK’s Master SPI Data Register Slave SPI Data Register
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12-Apr-11—9:34 AM SPI for 68HC12 2 University of Florida, EEL 4744 – File 19a © Dr. Eric M. Schwartz EEL 4744 EEL 4744 SPI Block Diagram Tech: Fig 14-11 3 University of Florida, EEL 4744 – File 19a © Dr. Eric M. Schwartz EEL 4744 EEL 4744 SPI Details • Message Length: 8-bits > Th ti t t i db lbf f d > The transmitter is not double buffered – Since SPI has an interrupt, the need for double buffering on the transmitter side is reduced (although not eliminated) – After 8 SCK clock times (after a transmission is started), the SPIF flag is set; this can generate an SPI interrupt >The receiver side is double buffered 4 University of Florida, EEL 4744 – File 19a © Dr. Eric M. Schwartz • Shift Register: MSB … LSB or LSB … MSB, your choice (set by LSBF bit in SP0CR1)
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12-Apr-11—9:34 AM SPI for 68HC12 3 University of Florida, EEL 4744 – File 19a © Dr. Eric M. Schwartz EEL 4744 EEL 4744 SPI Baud Register (SP0BR) • SPR2-SPR0 in SP0BR: SPI bit rate select (for master) > Master’sbi frequency: > Master s bit-frequency: –E-clock X, where X=2, 4, 8, …, 256 and X = 2( SPR+1) – For our 2Mhz E-clock Bit frequencies (f bit ): 1MHz, 500kHz, … 7.8kHz Byte frequencies (f byte =f bit /8): 125kHz, 62.5kHz, … 976 Hz Byte periods (T byte =1/f byte ): 8 s, 16 s, … 1.02ms 5 University of Florida, EEL 4744 – File 19a © Dr. Eric M. Schwartz 0 0 0 0 0 SPR2 SPR1 SPR0 SP0BR $00D2 76543210 00000000 RESET EEL 4744 EEL 4744 SPI Control Register 1 (SP0CR1) • SPIE enables the interrupt • SPE enables (turns on) the SPI system • SWOM: “Port S Wired Or Mode” all or nothing SWOM: Port S Wired Or Mode all or nothing > 0: normal; 1: Open drain • MSTR: 1-Master; 0-slave • CPOL (clock polarity); CPHA (clock phase) • SSOE enables the SS.L pin as an output on the master if SSOE = 1 and DDRS7=1 For a master, MSTR 6 University of Florida, EEL 4744 – File 19a © Dr. Eric M. Schwartz SPIE SPE SWOM MSTR CPOL CPHA SSOE LSBF SP0CR1 $00D0 RESET
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19a - 12-Apr-11-9:34 AM SPI for 68HC12 EEL 4744 EEL 4744...

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