32k8_SRAM_CY62256VN

32k8_SRAM_CY62256VN - CY62256VN 256K (32K x 8) Static RAM...

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CY62256VN 256K (32K x 8) Static RAM Cypress Semiconductor Corporation 198 Champion Court San Jose , CA 95134-1709 408-943-2600 Document #: 001-06512 Rev. *B Revised September 25, 2009 Features Temperature Ranges Commercial: 0°C to 70°C Industrial: –40°C to 85°C Automotive-A: –40°C to 85°C Automotive-E: –40°C to 125°C Speed: 70 ns Low Voltage Range: 2.7V to 3.6V Low Active Power and Standby Power Easy Memory Expansion with CE and OE Features TTL Compatible Inputs and Outputs Automatic Power Down when Deselected CMOS for Optimum Speed and Power Available in Standard Pb-free and non Pb-free 28-Pin (300-mil) Narrow SOIC, 28-Pin TSOP-I, and 28-Pin Reverse TSOP-I Packages Functional Description The CY62256VN [1] family is composed of two high performance CMOS static RAM’s organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE ) and active LOW output enable (OE ) and tristate drivers. These devices have an automatic power down feature, reducing the power consumption by over 99% when deselected. An active LOW write enable signal (WE ) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O 0 through I/O 7 ) is written into the memory location addressed by the address present on the address pins (A 0 through A 14 ). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high impedance state unless the chip is selected, outputs are enabled, and write enable (WE ) is HIGH. . A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 COLUMN DECODER ROW DECODER SENSE AMPS INPUTBUFFER POWER DOWN WE OE I/O 0 CE I/O 1 I/O 2 I/O 3 32K x 8 ARRA Y I/O 7 I/O 6 I/O 5 I/O 4 A 10 A 13 11 12 14 1 0 Logic Block Diagram Note 1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com . [+] Feedback
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CY62256VN Document #: 001-06512 Rev. *B Page 2 of 13 Pin Configurations Product Portfolio Product Range V CC Range (V) Power Dissipation Operating, I CC (mA) Standby, I SB2 ( μ A) Min Typ [2] Max [2] Max [2] Max CY62256VNLL Com’l 2.7 3.0 3.6 11 30 0.1 5 CY62256VNLL Ind’l 2.7 3.0 3.6 11 30 0.1 10 CY62256VNLL Automotive-A 2.7 3.0 3.6 11 30 0.1 10 CY62256VNLL Automotive-E 2.7 3.0 3.6 11 30 0.1 130 1 2 3 4 5 6 7 8 9 10 11 14 15 16 20 19 18 17 21 24 23 22 Top View Narrow SOIC 12 13 25 28 27 26 GND A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 WE V CC A 4 A 3 A 2 A 1 I/O 7 I/O 6 I/O 5 I/O 4 A 14 A 5 I/O 0 I/O 1 I/O 2 CE OE A 0 I/O 3 22 23 24 25 26 27 28 1 2 5 10 11 15 14 13 12 16 19 18 17 3 4 20 21 7 6 8 9 OE A 1 A 2 A 3 A 4 WE V CC A 5 A 6 A7 A 8 A 9 A 0 CE I/O 7 I/O 6 I/O 5 GND I/O 2 I/O 1 I/O 4 I/O 0 A 14 A 10 A 11 A 13 A 12 I/O 3 TSOP I (not to scale) Reverse Pinout 22 23 24 25 26 27 28 1 2 5 10 11 15 14 13 12 16 19 18 17 3 4 20 21 7 6 8 9 OE A 1 A 2 A 3 A 4 WE V CC A 5 A 6 A 8 A 9 A 0 CE I/O 7 I/O 6 I/O 5 GND I/O 2 I/O 1 I/O 4 I/O 0 A 14 A 10 A 11 A 13 A 12 I/O 3 TSOP I (not to scale)
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32k8_SRAM_CY62256VN - CY62256VN 256K (32K x 8) Static RAM...

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