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ex2_sol_f10 - EEL 47440 — Dr Gugel Last Name First Name...

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Unformatted text preview: EEL 47440 — Dr. Gugel Last Name ' First Name Keq Fall 201 0 Exam #2 UFID# ‘ 0 Open book and open notes, 90-minute examination to be done in pencil. - No electronic devices are permitted. - All work and solutions are to be written on the exam where appropriate. M Point System (for instructor and TA use only) Page 2 12 points filfke Page 3 ' 14 points Ina/H Page 4 20 points Mn?” Page 5 18 points 8" and”) Page 6 10 points C 0h». Page 7 26 points Er fr. Brought my Board l 3 points ' Y’dk J TOTAL I O 3 out of 103 Grade Review Information: (NOTE: deadline of request for grade review is the day the exam is returned.) — — — — — — — — — — — — K53 Read in 100“, characters from a PC via the USB port (SCI B) and write the characters to a SERIAL LCD at a rate of 1 character per 1 mSec. Repeat for every new 100 characters read in from the PC. You must read in all 100 characters before sending them out at the specified rate. Assume the PC sends 100 characters and then waits at least 1 second to send another group of 100 characters. 1.0 Assuming that we are using our lab's 15 MHz DSP board. design a system that will do the following: The SERIAL LCD has the following cenneclions: Pin 1 —> VCC. Pin 2 —> 6ND. Pin 3 —> Sin, Pin 4 —> ms The SERIAL LCD has the following functionality: When rcs is high. characters sent to the LCD go to the Command Register. The command register has the same functiom'commands as a typical 4 bit parallel LCD. When ICS ts low, characters sent to the LCD are written to the Data Register and therefore show up on the screen. The SERIAL LCD has a fixed communication protocol of 1 start bit. 1 stop bit' 7 data bits. 1 Odd parity hit and a BAUD Rate = 7.5K Hz 5 —-> for Cl .4» L6. Design Rules: 0 6 J 3 s A D . ( id A. Use UART SCI A on our DSP board to interface to Ihe Serial LCD. Ci“ flu-1' "fi ‘ B. Use TIMER 0 In an interrupt driven manner to set up the 1 msec timing interval. f) K“? C. Onca the TIMER 0 interrupt has been enabled. it show'd not be disabled for any reason. w (:1, 7‘; D. Use polling for all serial communications. Therefore only the Timer is interrupt driven. 1.1 Show the physical connections required on the LCD. Label all signals with as much detail as possible for maximum points. Le. Show the connections between the DSP and LCD! Show all LCD pin connections! {5 pt): PM = +33“ Prams = rxfimbrp P1132. " 6ND P1337”: 610/0 flflfi email}: LCD f5},- CMMM-‘Lefibu .- 1 2 Write the code to initialize the SCIA UART attached to the Serial LCD. Assume the stocks have been set up already for SCIB (USE). Sgecifg all Register Addresses Used. (3 pt.) M 69/02? rev 1% WWW/6 SW CM“ W 705’ 2 M“ 0v» res? 1% web/2’2}! 0/5!” flaw ml}: 743:1?” fl/aj‘m 5c 1/950: 5 0x 26 r Mala: 0x755" K15 mgggcru r7 3% ML #5 J;__ gull 5cm ad'afre _ . Sag/23am fl = O ' ”(é/«5 0): 7052— M [email protected]€L—_ j Mr sagzofi’j 5 E W"..— 1.3 Write the ASSEMBLY code to lnitiatize the TimerO Period Reg and the Prescaierf equal to 2. 4 pt.) coz. 715x/0" J9 .. M’) a 2500 men ”RD If " 0;! 653 ? féwbc’ :2 fMKQ/K‘Z- Q 09¢? plantar 'flageggma a5 exec? Page 2 Page Score = KW 1.4 Write the ASSEMBLY code to set-up the interrupt vector with the interrupt tabel called "TIMERELISR". Nan write the code to pre-Ioad the Timero registers and enable the interrupt. Assume this code will be pieced in the main routine. (T pt.) 0,19 flECTfi-K’L a gafér%#0 E (says fit: Mo!“ = @{CEb 0-5 3/5/9621 -" 0x, FFF f afar-v fzaje-fllffgj 521‘ M510”; 0x65 / i iflE/éfiie/ «P {cf é; 15% g ens/Me xii/.7 div-‘5 65.165; , 2’51: '9 5d 5% #0 g aha-Ne Cphjd'l mu Ma! #3212452 2‘ jut/,2, :53 a .5? 0x 00% fljat/ 22,4110! ,4" fingzg. me >516 j Kmart! of Andie, 44ft» swam 1.2 Mr: flm MM/ Jt‘flKO! #fiugz¢.—m€ J- ]:iwev W2 3 KW?! mr ‘? OyD‘fD I We M~v5¢u‘#/¢ jam W cm W ,s m . . use! i 03 ’( 1.5 Write the main routine code (ASSEMBLY) to pat! the USP UART and read in we characters sent from the PC via the i {n - unheard USB port. The first address of the 100 character buffer should be anDOD. Use AR? as the character counter : i t: 3;)“ use any required additional memory or flags at OKAUOU. You may assume that the DSP UART has already been J, mitialized to match the serial communication of the P {7 pt.) [fig [‘67 : Ago/0 In» .44."qu caff‘ WW: , Q Qxfioq) ; flat for! {clad-av- raecew 'ki’e J a}. 00 " W “9"”. - {3 5x Am! : 1'58 Kantian” ,qg/s oxgago - frets?— M»? ii?! Qaflwwa 5 02m: Manny»? Lenin? £2727 :- moo w _. acad’ Wk Kw! gag 2m— Age; 0:: AMD=j '/00dmv {I :35!“ I 1 CW flXF/L 46:01th {5 2011,} mg ._ ft & Pail ifnor‘sd [Madam/9M air / MM kw mm 55f . ‘ [pp-+2 7’3 hem ail oéz/gfl jAJC. £151, ' {MC {3" 05?: 29:67 ‘dec 60;?” ——__—;Mfl_.__ Cheat {F ”£750 Page 3 17 flat}; I; no?" 67' 3 Page Score = .‘9’ , r - . @ clmzK 100°“G{&"W 0‘5®’5‘“32;W£§ ‘ Qtrzz'wflmm Q‘mM-5 \ I, \lqfi'fi,‘\ . 127M; ,grge : £69 Write th ASSEMBLY code required for the interrupt handler to send out the 100 characters at the desired 1msac per character rate. (6 pi.) Chat}: foocl’uv 106/7 (ck/95m? Ml (Amok l‘iag é: END 1¥cjedrwflefga 09»de- étade gr fray-«r WM} ‘ W096“? 093 V” [€64 W? “54.32 #0119 p Y \W , W :L 17v:— £24445? fsiwté 0x330} i and or «transmlimj Calms (5 Cheat ,p E2fiy :- oxgmflm; fir ”crawl! bra—nah fa Em? x¥ gold! clear (22/9630 /00 Uta-I {£9 (a; 35 chat/Wily?” a.) “life Oxfw -> 02429619! j 9 1.8 A student is having problems with his Serial LCD display and so he write code to continuously write out a 'i” {37 Hex in ASCI!) for debug purposes. They then connect a digital scope to the Sin pin of the LCD. Sketch the expected waveform that should he observed for one character. The Y axis should be voltage and the X axis should be time. Label the voltage values for highflow on the Van‘s and the expected period for one bit. (8 pt.) - “'55.: \ Page 4 ' Page Score = ' 2.0 A student would like to connect two DSP boards (DSPmA and DSP_B) together using the DATA BUS for communication between the DSP boards. Assuming the communication will be iii-directional and 8 bits. draw the — additionally circuitry required below to facilitate this communication. Note: Extra hardware can be added to the DSP and additional DSP pins can be used for communication control and data acknowledgement. The best design will receive the most points. Design for optimal speed in communication first and then reduced component cost. (14 pt.) D5? A 710 Cow: D8199" +4, 55? B afllopflepiol 619301?” email) 1 [/3 Credit? Stile“ QPJOLWC‘imos liar u R t" ' A ‘3 amosw GP'OZ 1" ‘1 {of C {7&1} 2.1 Describe how a word can be sent from DSP_A to DSP_B using your interiace above and vice versa a word from DSP_B backto DSP_A. (4 pt.) GPIO = Dail'fic GPIDZ = X1558. 19059le , ’t (D DSP 4‘” indie: M3. “toddler 4:153le Dafofa 1i— wajfg fay Ang C?) DSP Jak2. {ted}: chi-.5; Mari? AOL if wflii‘: fir 001-ka ‘l'o 5° “WM-t 3 bard] Vembxl‘fls 501?va a? mi; 5w flak in aw ‘ ED DQF’l‘Z sacs Dafw’fx Owe 5; Who‘d“ AC!“ 7t D3? fl" (USO heals +0 M £5? DOJI’RTX. 1Com ‘H‘? 0117“" 099! No 50542,; )e . no new .1: bd‘ at»: 1:25 i. M 5M" T 50 MN: Dwfl po+ WmoriiiPageScore= Page 5 3.0 Given the following Microprocessor Timing Diagram. answer the questions that follow. u? Write Cycle uP Read Cycle Rl-W I I I ! , . l , _ vDS 915:0 _ _ . W" . . ‘ , x ’7 ‘SRAM‘CE fip r2..- ‘\mukW0W'° 5 NH? 4; ’ ' l. sfim 7 to 6347s delf MP ’7 r0 3.1 Given any number of 8Kx16 SRAMs create a block of 16K memory' in the highest 16K of uP's memory map. Assume full address decoding and that the —OE signal must be false an a write cycle and true on a read cycle. Show the SRAM connections and the decoding circuitry. Label all signals. ('1 pt.) IS in 196 “OS 3.2 Assuming a zero propagation delay for the decode circuitry draw the -SRAM CE signal for a memory that is being written to and then read from. DRAW THE —SRAM_CE SIGNAL !N THE TIMING DIAGRAM ABOVE. (3 pt.) fiven the following timing diagram above and the DSP 8- SRAM fipeciflcations below. answer the questions that follow. fl“ 3 eclflbations 8. Re ulramonts -WRITE C etc M m Specifications 8. Reguirements - READ Cycle RI—W 8: Address True to ~—DS True = 30(min)l35(max) RI—W 8. Address True to —DS True = 30(minjl35(max} -DS Width = 44148. RI-W False to —DS False = 10113 -DS Width = 44MB. W's-Fem AddressIData Hold after Rl-W False = 31’? ' Data Hold After —DS False a nine maximum Data Setup Before RI-W False = 12115 Data Setup Before —DS False = Tine maximum SRAHI Sgacifieatlons 8. ngulrements - Write Crete SRAM Sgeclficatlons a. Reguiraments — Read gels Rl—W 8: Address True to —CS True = 20lno maximum RI-W & Address True to ~68 True = 201m maximum -CE Width = 30lno maximum -CE Width = 30an maximum Rl-W 8t Address True to -OE False = 20ino maximum Rf-W & Address True to ~0E True = 20fno maximum Data Setup time = Tina maximum Rl-W, —CE. —OE False (whichever first] Hold time = 317 Hold time = Gino maximum Enable SRAM Memory Access time = 9“? Page 6 Page Score = ((53 3.3 What is the CPLD propagation delay (0,”) range thatwill meet the USP 0 SRAM WRITE timing specifications using the worst case timing specifications? (5 pt.) .- 1/4,.7'? {Cyan/.20 3572 {WZO'EO 7 3.4 What is the CPLD propagation delay (tam) range that will meet the DSP a SRAM READ timing specifications using the worst case timing specifications? (5 pt.) 45/«i7az7bestmif 12:; 202% L020 3.5 What is the final range for the propagation delay for the PLD such that it will work for both a WriteIRead cycle? (2 pt.) >{C £20 20 3.6 if the SRAM timing specification "Rf-W & Address True to -CS True= 20lno maximum" turns out to be "Rf—W & Address True to —CS True= 401110 maximum”. what will we have to do to use this SRAM? (3 pt.) /m’fch Matters 015% ”441/ #1" db ”ml? Wag: 4.0 Miscellaneous Memory Related Questions 4.1 A student connects (2} 64MB SRAMs to the address and data bus to create a singie 64Kx16 block of SRAM. Then to save logic they connect—CS7 to to the -CS signals on each SRAM. Upon writing a test program that places a different value (16 hit counter number. to addresses O—FFFF contain data U—FFFF) at every address in memory, they notice a duplication of data when scrolling with the debugger’s memory window function How many times total should they see the same value if they scroll through the entire memory range denoted by —CST? Note: You may assume that —RD :5 connected to -OE on the SRAM and -—WR' is connected to RI-W on the SRAM. (3 pt ) 20000032”: (gift-pg 6’7,“ A" 314: l0 00334:? ZFFFFF {“410 A190 [(9 {M}; 4.2 In the above example, the student decides to connect a LogiclState Analyzer to view a short test program that has been copied over to this block of memory. See the short list file below. 00000001 BDZO t1: MOVL XARO,#0X20ABCD 00000002 0000 00000003 20A9 nov AL,#0X1234 00000004 1234 . 00000005 96C0 MOV *XRRO,AL :THIS TAKES 2 CYCLES TO EXECUTE THIS INSTRUCTION 00000006 EFFB a t1,unc it the student connects an LSA to the SRAM address lines, data lines. -OE. -CS and Rf-W lines. draw what they should expect to see tor the two cycles that correspond to execution of the instruction "MOV ‘XARD,AL“. Show bus values! 'gnr-w (rill?) 9 433 I; : .l I ‘ ~ ,5 .05 (Alb) “Hi-.4 ; 1 I AddrBus . 200005 . § . 2014803; i I M b I c ‘ j 1 fiSData Bus : 4660': '5 I239; ‘ Page 7 . i Page Score— " MD 0(7wa i wlZI’I‘E M70 ...
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