lab4_s11_IO_port_keypad

lab4_s11_IO_port_keypad - University of Florida Electrical...

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University of Florida EEL 4744 – Spring 2011 Dr. Eric M. Schwartz Electrical & Computer Engineering Dept. Revision 7 Colin Watson, TA Page 1/5 Lab 4: Keypad and I/O Port Expansions 28-Feb-11 OBJECTIVES To explore and understand the implementation of memory-mapped I/O. Add an 8-bit input port and an 8-bit output port. To understand how a keypad functions as a raster scan input device and to learn how to interface a keypad to a microprocessor. REQUIRED MATERIALS(needs update) Wire wrap tool, multi-meter, DSP board 1 - 74HC573, 1- 74HC574, 1 keypad, 2 - 0.1 F bypass capacitors, wire wrap 1 - 10 - pin wire - wrap socket (get from TAs du ring their office hours BEFORE your lab) Read/save the following document: o Timing diagram on SPRU949D (pg 33-36) o GPIO Multiplexing and PCLKCR3 description, in SPRUFB0D o Spec sheets for 74HC573 and 74HC574 PRELAB REQUIREMENTS It is required that you make a flowchart or write pseudo- code before writing any program in this course. This will help you formulate a plan of attack for the code. Submit these flowcharts/pseudo-code as part of your prelab requirements. Comments in your programs are also required. The Pre- lab Report Guidelines state that “All code should be commented to a level that someone how can readily understand the purpose of each section if not each line of code.” Part A: Input/Output Ports, General Description The DSP and other many other microprocessors have several input/output (I/O) pins, often with multiple pins grouped together and called input/output ports. Each of the I/O pins typically has additional non-I/O features that can be utilized as an alternative to general I/O. Therefore, it would be useful if we can “free up” these pins for their special use by adding other memory-mapped I/O ports. 1. Generate the necessary chip-enable equations to implement one 8-bit input port and one 8-bit output port. Both ports should both be mapped to address 0x4000 and mirrored at addresses 0x4001 through 0x47FF. (For this lab ONLY , ignore address pins A21 through A16. For subsequent labs, we will add other external components that will overlap the addresses specified for the I/O ports unless we include the address pins A21 through A16. Failure to utilize these pins in this case will cause damage to your devices.) Use partial address decoding (also known as reduced-address decoding). Tri-state buffers MUST be used for input ports and flip-flops should be used for output ports. Two chips included in your kit, the 74HC573 and 74HC574, contain the tri-state buffers and flip-flops. 2. Use Quartus to design a circuit to add both the input and output port chip-enable equations to your CPLD. Use either schematic entry or VHDL to design your
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lab4_s11_IO_port_keypad - University of Florida Electrical...

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