AsicDesign-R2011V1

AsicDesign-R2011V1 - 18-5-2011 Challenge the futureDelft...

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Unformatted text preview: 18-5-2011 Challenge the futureDelft University of Technology Asic Design ET 4351 Alexander de Graaf, EEMCS/ME/CAS 2 ASIC Design: Backend | 100Outline.1.Design flow 2.Synthesis 3.Place & Route 3 ASIC Design: Backend | 1001.Design flow 4 ASIC Design: Backend | 100Design flowgraph Tools Synthesis: Synopsys Design Compiler Place & Route: Cadence SOC Encounter 8.1 Process UMC L90 SP Standard cell library Faraday: fsd0a_a_generic_core fod0a_b25_t25_generic_io Synthesis Place&Route VHDL Source Gate Level Netlist Std Cell Lib Area Timing Constraints LayoutGDSII Gate Level Netlist Area Timing Constraints 5 ASIC Design: Backend | 1002.Synthesis 6 ASIC Design: Backend | 100Synthesis flow Design Compiler Flow Asic Synthesis Flow 7 ASIC Design: Backend | 100Synthesis Transformations 8 ASIC Design: Backend | 100Load Design and Libraries Analyze Reads source code files (Verilog or VHDL RTL) Checks syntax and issues errors/warnings Converts both Verilog and VHDL files into intermediate binary format files, placed in CWD Can use define_design_lib to redirect the files/directories to a sub-directory Elaborate Reads the intermediate .pvl files and builds the GTECH design in DC memory (unmapped ddc format) Sets the current design to the specified design Links and auto-loads the specified design Allows specification of parameter values: elaborate MY_TOP -parameters N=8, M=3. 9 ASIC Design: Backend | 100Area and Timing Constraints Static Timing Analysis (STA) Modeling clocks Constraining input paths Constraining output paths Environmental attributes 10 ASIC Design: Backend | 100Static Timing Analysis Main steps of STA Break the design into sets of timing paths Calculate the delay of each path Check all path delays to see if the given timing constraints are met Four types of paths Reg Reg PI PO Start point End point Combinational logic 11 ASIC Design: Backend | 100Static Timing Analysis Path-based STA Calculate the Arrival Time (AT) by adding cell delay in timing paths Check all path delays to see if the given Required Arrival Time (RAT) is met 12 ASIC Design: Backend | 100Static Timing Analysis (Cell delay) 13 ASIC Design: Backend | 100Static Timing Analysis (Setup Time) To meet the setup time requirement: Trequire>= TarrivalReg to Reg Tarrival= Tclk1+ TDFF1(clk->Q) + TpathTrequire= Tclk2- TDFF2(setup)Tslack= Trequire- TarrivalTDDF1+Tpath Tarrival Trequire Tslack Tsetup Clk_source clk1 clk2 Reg Reg clk2 clk1 14 ASIC Design: Backend | 100Static Timing Analysis (Setup Time) PI to Reg Tarrival= TPI(delay) + TpathTrequire= Tclk1 TDFF1(setup)Tslack= Trequire- TarrivalTpath Tarrival Trequire Tslack Tsetup Clk_source clk1 Reg clk1 PI TPI 15 ASIC Design: Backend | 100Static Timing Analysis (Setup Time) Reg to PO Tarrival= Tclk1+ TDFF1(clk->Q) + TpathTrequire= Tclk1- TPO(output delay)Tslack= Trequire- TarrivalTDDF1+Tpath...
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This note was uploaded on 07/09/2011 for the course ECE 322 taught by Professor Joy during the Spring '11 term at St. Martins.

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AsicDesign-R2011V1 - 18-5-2011 Challenge the futureDelft...

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