ctp_cdnlive2005irdrop

ctp_cdnlive2005irdrop - IR Drop and Electromigration...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
1 IR Drop and Electromigration Analysis with Ultrasim Power Network Solver in the VAVO/VAEO flow Xiaodong Zhang, Xiaohai Wu, Qing Zhang, Jun Kong, Stefan Wuensche, Lifeng Wu, Bruce McGaughy Nanometer Solutions Devision Cadence Design System San Jose, California Lalit Garg, Paddy Mamtora Design For Manufacture Devision Cadence Design system San Jose, California Abstract: With CMOS process technology scaling down to 130nm and below, IR-drop and electromigation (EM) effects become significant design considerations. Decreasing power supply voltages due to IR drop, and signal degradation due to EM effects easily causes design failures which need to be analyzed early in the design process. Cadence’s Virtuoso Analog VoltageStorm Option (VAVO) and ElectronStorm Option (VAEO) powered by Virtuoso Ultrasim simulator power network solver (UPS) offer a complete solution for IR drop and electromigration analysis. Ultrasim UPS, a linear solver integrated into UltraSim, analysis dynamic IR and EM effects in analog, mixed signal, memory, and digital circuits. The required high performance and capacity is achieved by combining UPS with the advanced fast spice technologies built into Ultrasim. In the VAVO/VAEO flow Ultrasim UPS is used as simulation engine while post-processing of the IR and EM data is done with VAVO/VAEO. VAVO analysis the IR drops in the power net, while VAEO checks for EM problems on signal nets. Both tools are integrated into the Analog Design Environment, and the extraction of the interconnect parasitics is performed with Assura RCX. VAVO/VAEO display IR drop and EM results as colored map in the layout, and as textual report, which allows cross-probing to the layout. Colored map and cross probing make it easy to debug and identify IR drop and EM problems. The paper introduces the VAVO/VAEO flow and the UltraSim UPS technology, discusses the IR drop and EM analysis features, and illustrates its application on a PLL design.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 Section I. Introduction With CMOS process technology scaling down to 130nm and below, IR-drop is becoming an extremely important phenomenon determining the performance and reliability of ULSI designs. The IRdrop effect manifests itself in the power grid distribution networks and can adversely influence the performance of the signal nets, including timing, signal integrity and noise. Voltage drops become even more critical as supply voltages fall to 1 V dc and below. Meanwhile, increased power demanded on ever shrunk chip size causes higher current densities within the power routing. High currents also induce EM effects in which metal lines begin to wear out during a chip's lifetime. To minimize the rate of EM, peak, average and rms current densities of both power and signal nets need to be calculated. A complete picture of power grid integrity can only be obtained when IR drop, ground
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 07/09/2011 for the course ECE 322 taught by Professor Joy during the Spring '11 term at St. Martins.

Page1 / 7

ctp_cdnlive2005irdrop - IR Drop and Electromigration...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online