ctp_cdnlive2005irdrop - IR Drop and Electromigration...

Info icon This preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
1 IR Drop and Electromigration Analysis with Ultrasim Power Network Solver in the VAVO/VAEO flow Xiaodong Zhang, Xiaohai Wu, Qing Zhang, Jun Kong, Stefan Wuensche, Lifeng Wu, Bruce McGaughy Nanometer Solutions Devision Cadence Design System San Jose, California Lalit Garg, Paddy Mamtora Design For Manufacture Devision Cadence Design system San Jose, California Abstract: With CMOS process technology scaling down to 130nm and below, IR-drop and electromigation (EM) effects become significant design considerations. Decreasing power supply voltages due to IR drop, and signal degradation due to EM effects easily causes design failures which need to be analyzed early in the design process. Cadence’s Virtuoso Analog VoltageStorm Option (VAVO) and ElectronStorm Option (VAEO) powered by Virtuoso Ultrasim simulator power network solver (UPS) offer a complete solution for IR drop and electromigration analysis. Ultrasim UPS, a linear solver integrated into UltraSim, analysis dynamic IR and EM effects in analog, mixed signal, memory, and digital circuits. The required high performance and capacity is achieved by combining UPS with the advanced fast spice technologies built into Ultrasim. In the VAVO/VAEO flow Ultrasim UPS is used as simulation engine while post-processing of the IR and EM data is done with VAVO/VAEO. VAVO analysis the IR drops in the power net, while VAEO checks for EM problems on signal nets. Both tools are integrated into the Analog Design Environment, and the extraction of the interconnect parasitics is performed with Assura RCX. VAVO/VAEO display IR drop and EM results as colored map in the layout, and as textual report, which allows cross-probing to the layout. Colored map and cross probing make it easy to debug and identify IR drop and EM problems. The paper introduces the VAVO/VAEO flow and the UltraSim UPS technology, discusses the IR drop and EM analysis features, and illustrates its application on a PLL design.
Image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon