custom ic - A Top Down Design Methodology for Mixed-Signal...

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A Top Down Design Methodology for Mixed-Signal Integrated Circuits using the VppSim Simulator CDNLive! 2006 Session Track: Custom IC Design Session Number: 3.4 Michael Perrott Massachusetts Institute of Technology September 2006 Copyright © 2006 by Michael H. Perrott All rights reserved.
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2 A Modern “Analog” Custom IC ± A 2.5 Gb/s CDR for high speed links - Analog amplification and phase sensing - Digital filtering and calibration - RF clock generation (2.5 GHz) ± How do we design such chips?
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3 Simplified View of a Top Down, Mixed-Signal Design Flow System Design Architecture Circuit Verification Digital Circuit Design Analog Circuit Design Digital Circuit Verification Analog System Verification High Level Analysis System Level Test Vectors Schematic Creation Code Creation Extracted Layout Creation PVT Corners Monte Carlo Digital Test Vectors Timing Checks
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4 The Many Simulation Tools Involved … System Design Architecture Circuit Verification Digital Circuit Design Analog Circuit Design Digital Circuit Verification Analog System Verification Matlab/Simulink ADS SPICE Verilog/VHDL Verilog AMS AMS Designer ???????? Popular Tools
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5 Goal: Create a Universal Simulator ± The challenges of developing the Managing Kernel - Difficult to match up simulator signals at their boundaries without overly complicating the life of the user - Difficult to maintain fast simulation speed - Difficult to retrain designers on a new tool with a new flow Managing Kernel SPICE Matlab Verilog VHDL System Designer Analog Designer Digital Designer
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6 A Different Approach ± Look for commonality among simulators to allow “universal” simulation models to be used - C++ provides one such hook ± Allow designers to use their tool of choice while sharing “universal” simulation models SPICE Matlab Verilog VHDL C/C++ Mex functions C/C++ PLI Calls C/C++ PLI Calls (Verilog AMS Key idea: bootstrap into existing simulators
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7 The VppSim Simulator Greatly Simplifies This Process ± Graphically driven generation of simulator blocks based on a C++ primitive library Automatic wrapper generation AMS Designer Matlab NCVerilog Analog Designer System Designer Digital Designer Mex Function Verilog PLI Verilog PLI Calls Cadence Schematic Entry C++ primitive library Simulation parameter file
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8 C++ Code Can Also Be Directly Simulated ± Advantage: - Very fast! Automatic wrapper generation AMS Designer Matlab NCVerilog Analog Designer System Designer Digital Designer Mex Function Verilog PLI Verilog PLI Calls Automatic C++ system generation Cadence Schematic Entry C++ primitive library CppSim Simulation parameter file
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9 Using VppSim Within an Analog Design Flow Automatic wrapper generation AMS Designer Analog Designer Verilog PLI Calls Cadence Schematic Entry C++ primitive library SPICE primitives Verilog-A primitives Verilog primitives VHDL primitives ± C++ behavioral models allow accurate representation of:
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custom ic - A Top Down Design Methodology for Mixed-Signal...

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