ddf1011 - Faculty of Electrical Engineering, Mathematics...

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Unformatted text preview: Faculty of Electrical Engineering, Mathematics and Computer Science Circuits and Systems Mekelweg 4, 2628 CD Delft The Netherlands http://ens.ewi.tudelft.nl/ ET4351-2011-01 Tutorial Digital Design Flow For EDA tools: Mentor Modelsim Synopsys Design Compiler Cadence SoC Encounter Ir. A.C. de Graaf Ing. H.J. Lincklaen-Ariens Dr. ir. T.G.R van Leuken Preface This document describes the top-down design flow of the implementation a SoC design. Start- ing from a example HDL description the designer is guided through all the design steps to tapeout GDS2 layout description. This tutorial is derived from ”Top-Down digital design flow” version 3.1 (November 2006) by Alain Vachoux, Microelectronic Systems Lab EPFL, Lausanne, Switzerland. Ir. A.C. de Graaf Ing. H.J. Lincklaen-Ariens Dr. ir. T.G.R van Leuken Delft, The Netherlands My Graduation Date iii iv Contents Preface iii 1 Introduction 1 1.1 Top-down design flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Design project organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 EDA tools and design kit configuration . . . . . . . . . . . . . . . . . . . . . 4 1.4 Installation of the FARADAY design kit . . . . . . . . . . . . . . . . . . . . 5 1.5 VHDL example: Adder-subtractor . . . . . . . . . . . . . . . . . . . . . . . . 7 1.6 Text editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.7 Design flow steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 VHDL and Verilog simulation 13 2.1 Starting the Modelsim graphical environment . . . . . . . . . . . . . . . . . . 13 2.2 Simulation of (pre-synthesis) RTL VHDL models . . . . . . . . . . . . . . . . 14 2.3 Simulation of the post-synthesis VHDL model with timing data . . . . . . . 17 2.4 Simulation of the post-route Verilog model with timing data . . . . . . . . . 18 3 Logic synthesis 23 3.1 Starting the Design Vision graphical environment . . . . . . . . . . . . . . . 23 3.2 RTL VHDL model analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3 Design elaboration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4 Design environment definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5 Design constraint definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6 Design mapping and optimization . . . . . . . . . . . . . . . . . . . . . . . . 29 3.7 Report generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.8 VHDL/Verilog gate-level netlist generation and post-synthesis timing data (SDF) extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.9 Design constraints generation for placement and routing . . . . . . . . . . . 39 3.10 Design optimization with tighter constraints . . . . . . . . . . . . . . . . . . 41 3.11 Using scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4 Standard cell placement and routing...
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This note was uploaded on 07/09/2011 for the course ECE 322 taught by Professor Joy during the Spring '11 term at St. Martins.

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ddf1011 - Faculty of Electrical Engineering, Mathematics...

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