tutor1 - 1 Tutorial 1 - Introduction to ASIC Design...

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Unformatted text preview: 1 Tutorial 1 - Introduction to ASIC Design Methodology ECE-520/ECE-420 ~ Spring 1999 ~ Rev. 99.1 Dr. Paul Franzon, Scott Perelstein, Amber Hurst-------------------------------------------------------------------------------------------------------------------- 1 Introduction: Typical ASIC design flow requires several general steps that are perhaps best illustrated using a process flow chart: Figure 1: Process Flow Chart No HDL Design Capture HDL Design Synthesis No Design Implimentation No Logic & Timing Netlist Verified? Floor Planning Layout Verified? Function & Timing Design Specification Behavioral Description RTL Description Functionality RTL Verified? Verification Vectors RTL to Logic Yes Logic Optimization Logic to Technology Constraints Constraints Optimization Timing/Area Scan Path Insertion & Test Vector Generation Place & Route Physical Layout Yes Chip Production Yes 2 This tutorial is meant only to provide the reader with a brief introduction to those portions of the design process that occur in the HDL Design Capture and HDL Design Synthesis phases, and a brief overview of the design automation tools typically used for these portions of the design pro- cess. The detailed methodology and strategies required to produce successful designs will be dis- cussed throughout the course lectures. This tutorial is broken up as follows: Section 2 is an overview of the design, synthesis and verification process Section 3 is an overview of the tools to be used Section 4 discusses pre-synthesis simulation and verification using Verilog. This step is important to ensure that your Verilog input for Synopsys is correct. Section 5 discusses logic synthesis using Synopsys. This is the step in which the Ver- ilog code is converted to a gate level design. Section 6 discusses post-synthesis simulation and verification using Verilog. This sim- ulation is run to check that the above two steps were correctly conducted. Section 7 discusses post-synthesis timing verification using Cadence Pearl. This timing verification is carried out as a check on the timing of the gate level design produced by Synopsys. Section 8 discusses how to run these tools using scripts. Most of the discussion in Sec- tions 4-7 are centered on running these tools interactively. Sometimes these tools can take a long time to run and running the tool in batch mode using a script is useful. Section 9 summarizes how to run the tools remotely. You can do all of the stepts above over a telnet session if you want. Section 10 discusses the Veriwell PC Verilog simulator. You can download this simula- tor and use it instead of Verilog-XL for pre-synthesis simulations....
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This note was uploaded on 07/09/2011 for the course ECE 2 taught by Professor Nitin during the Spring '11 term at St. Martins.

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tutor1 - 1 Tutorial 1 - Introduction to ASIC Design...

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