J7_return_current_paper_I_manager_camera

J7_return_current_paper_I_manager_camera - RESEARCH PAPERS...

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ANALYSIS OF INDUCTIVE EFFECTS OF ON-CHIP AND ON-BOARD RETURN CURRENT PATH FOR PERFORMANCE DEGRADATION MODELING IN VLSI DESIGN INTRODUCTION As the operating frequencies continue to rise in contemporary integrated circuits, inductive effects of interconnects must be included in the designing process. These inductive effects create noise in the power distribution network, ringing, overshoot/undershoot and reflection problems. Due to inductance being a loop phenomenon, the distribution and path of return currents must be known in order to avoid signal integrity problems. At high frequencies, in order to minimize the loop inductance, the return currents are confined to the nearest reference plane and follow the signal current closely. Any discontinuity in the return path causes the inductance to grow and results in the degradation of the signal. These discontinuities might be caused due to various reasons such as vias on the signal trace or high speed signal crossing multiple voltage reference planes on the same layer. In this paper the authors simulated the path of return currents on solid and split reference planes and obtained useful results for the distribution of return currents on a printed circuit board. The JEFFREY FAN ** By same observations can be applied to “on-chip” return current analysis. Some constructive effects of the inductance such as improved transition time and reduced dynamic power consumption [9] are also highlighted. The rest of the paper is as follows: related research work is presented in section 1, section 2 presents the theory, section 3 contains the details of the experiment, section 4 explains the transmission line model, section 5 describes on-chip inductance, section 6 presents the result and the last is the conclusion of the paper. 1. Related Work There has been much research into the inductive properties interconnects both on-board and on-chip. Arora et al. [1] reviewed different approaches to model the on- chip wire inductance and discussed methods to assess the inductance with special reference to return current path. Research in [2] presented an efficient performance optimization technique for distributed RLC interconnects and illustrated the implications of technology scaling on wire inductance. Signal integrity aware design techniques * Ph.D. Student, Florida International University, U.S.A. Assistant Professor, Department of Electrical and Computer Engineering, Florida International University, Miami, FL, USA. ** ABSTRACT As the dimension of interconnects in Integrated circuits has become dominant, the inductive effects of the wires cannot be ignored anymore. At high frequency, the return current distributes itself close to the signal path and any increase in the inductance of the return path hampers signal integrity. The multi-layered Power Distribution Network (PDN) is stressed when many devices draw current simultaneously, creating noise in the supply rails. This high speed current not only causes ground bounce and power supply sag but it also needs a low inductance return path. Since high frequency
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J7_return_current_paper_I_manager_camera - RESEARCH PAPERS...

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