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AUTOMATIC LAYOUT DESIGN FOR POWER MODULE Puqi Ning 1,3 IEEE Student Member Fred Wang 1,2 IEEE Fellow Khai Ngo 3 IEEE Senior Member 1 Oak Ridge National Laboratory Power Electronics & Electric Machinery Knoxville, TN 37932 USA 2 Department of Electrical Engineering and Computer Science The University of Tennessee Knoxville, TN 37996 USA 3 Center for Power Electronics Systems Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg, VA 24061 USA Abstract —The layout of power modules is one of the most important elements in power module design, especially for high power densities, where couplings are increased. In this paper, an automatic design process using a genetic algorithm is presented. Some practical considerations are introduced in the optimization of the layout design of the module. Abstract —Layout, genetic algorithms, parasitic parameters I. INTRODUCTION Parasitic parameters in a module have a detrimental effect on the switching loss and dynamic behavior [1]. They cause voltage overshoot, affect blocking voltage requirements of the power devices, and influence device switching losses. These phenomena are exaggerated when the density increases. In addition, power integration decreases distances, resulting in a bigger impact on the coupling of the current conduction path. To ensure high efficiency and high performance of a high-density power module, efforts are required in the layout design [2]. There are basically two important layout design considerations. First, when the switching frequency is high, large voltage spikes result due to the high di/dt. By reducing the parasitic parameters, the magnitude of these voltage spikes can be reduced [2]. Second, the parasitic parameters between paralleled devices need to be balanced. This helps to achieve equal current distribution in parallel devices, consequently affecting the performance of the whole module. As described in Fig.1, the layout design procedure is usually based on design iterations. Each cycle can generate a layout design result, which can then be compared with other design results. After several iterations the best layout can be chosen from the design candidates. Usually even the best layout candidate is not the best selection for the whole design space. The final selected result still requires a superior layout and will be beneficial in achieving power loss reduction. During the design iterations, devices and power terminals, which are the basic components in layout design, first are geometrically placed by considering the electrical connections. The second step is the routing process, in which the dies and the pads are connected with the copper traces and the wire bonds. Then the parasitic parameters in the designed layout can be
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