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Unformatted text preview: consistency performance calculation. paging, virtua memory 6. IO, buses CH 11, Week11 slides Basic bus design address data control: :polled IO, interrupt IO processing modes (kernel user) status register, mode bit, CWD in Intel), mode switch, hardware interrupts, service interrupts software interrupts, priorities, DMA, bus Masters, frontside bus, backside bus PCI bus EISA bus Bus bridge, 7. architecture CH 12, Week12 slides types, design with chips,cache: direct mapping, associative, bock set sot collision, data consistency performance calculation.paging, virtua memory Bus interface unit, prefetch queue,programming implications pipelining, potential speedup, effect of a jump, data stall, Harvard architecture implementation....
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This note was uploaded on 06/30/2011 for the course SOEN 228 taught by Professor T.fancott during the Winter '11 term at Concordia Canada.
- Winter '11