228_FINAL_Study_Guide - consistency performance...

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Department of Computer Science and Software Engineering Concordia University SOEN228 Computer Hardware FINAL study Guide Date: April 6 , 2011 1. Register Transfer Language CH 6,77, Week 5,6 slides Simple transfers involving memory, MAR, MDR, IR, PC, some general purpose registers (A, B) Parallel operations 2. Assembly Language conceecpts CH 87, Week 7,8 slides Addressing modes, segments, data definition, labels, system calls 3. Intro to Architecture CH 6,7, Week 8 slides Flags, condition codes, inte l registers, intel op code design, implementation of immediate, indexed, indirect addressing modes in intel architecture. 4. Stacks, calls, local variables CH 6.11,8 Week 9 slides Stack operations, local variables, call, return. Stack pointer base pointer pass by reference, pass by value 5. memory CH 9, 10, Week10 slides types, design with chips,cache: direct mapping, associative, bock set sot collision, data
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Unformatted text preview: consistency performance calculation. paging, virtua memory 6. IO, buses CH 11, Week11 slides Basic bus design address data control: :polled IO, interrupt IO processing modes (kernel user) status register, mode bit, CWD in Intel), mode switch, hardware interrupts, service interrupts software interrupts, priorities, DMA, bus Masters, frontside bus, backside bus PCI bus EISA bus Bus bridge, 7. architecture CH 12, Week12 slides types, design with chips,cache: direct mapping, associative, bock set sot collision, data consistency performance calculation.paging, virtua memory Bus interface unit, prefetch queue,programming implications pipelining, potential speedup, effect of a jump, data stall, Harvard architecture implementation....
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This note was uploaded on 06/30/2011 for the course SOEN 228 taught by Professor T.fancott during the Winter '11 term at Concordia Canada.

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