SOEN_228_11w_Tutorial_Notes_Jan_31

SOEN_228_11w_Tutorial_Notes_Jan_31 - produce asset to 1 set...

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Department of Computer Science and Software Engineering Concordia University SOEN228 Computer Hardware Tutorial notes Date: January 31, 2011 Refer to assignment 2 Question 1 a)Design a logic circuit to translate a BCD code to a cyclic code using a PLA. Do not draw the PLA, but show your design using a table representing the PLA inputs as: a,b,c,d, and the outputs as: w,x,y,z Example from slides (wk3)
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Question 2 a)Analyze the behaviour of the following asynchronous sequential circuit. Note that q indicates the present output and Q indicates the next output (after the state transition). Explain the behaviour of the circuit. Q = a’(b’+q’) Example Q = ab + aq Draw 3 variable K-map ab q 00 01 11 10 0 0 0 1 0 1 0 0 1 1 Analysis ab = 11 set to 1 ab = 00 set to 0 ab =10 memory Conclusion it works – ab = 01 not a usable combination Question 3 Design an SR flip flop using NAND gates and inverters. Show the Karnaugh map of your design and explain which input combinations
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Unformatted text preview: produce asset to 1, set to 0, and a memory state. Which input combinations cannot be used. SR q 00 01 11 10 1 1 1 1 Equation: Q = SR’ + R’q = R’(S+q) Then draw using NANDs Question 4 Design a JK flip flop using NAND gates and inverters. Use a master-slave design, and describe the sequence of operations of the master and the slave. Use a master slave design using NANDs as above Question 5 Design a synchronous binary counter with 6 states, from 000 to 110 and then back to 000. Use D flip flops and any gates and inverters you need. Show all steps in your design, from the truth table to the circuit. Example: count 00 – 01-11-10 d1 d2 D1 D2 00 1 01 1 1 11 1 10 Input equations: D1 =d2 D2 = d1’ Example2: count 00 – 11-10-01 d1 d2 D1 D2 00 1 1 11 1 10 1 01 Input equations2: D1 = d1’ d2’ + d1 d2 D2 = d1 d2’ + d1’ d2...
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SOEN_228_11w_Tutorial_Notes_Jan_31 - produce asset to 1 set...

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