SOEN_228-11_week5_slides

SOEN_228-11_week5_slides - SOEN 228/4 2011 T. Fancott Week5...

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SOEN 228/4– 2011 T. Fancott Week5 Basic Principles RTL Architectural concepts
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Storage The basic element DATA DATA SELECT select R/W R/W ONE BIT(0 OR 1), (0 VOLTS OR 5 VOLTS) ONE BYTE: 8 BITS ADDRESSED AS ONE UNIT clock clock
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Addressing Decoder Decoder Binary in e.g. 101 Selector wires out line 5 for 101 Selector Selector Binary in Selected address recognized USED TO ADDRESS MEMORY ELEMENTS USED TO ADDRESS I/O INTERFACES
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register operations register Registers immediately available to the ALU - example: ADD AX, DX clock Set up Transfer edge in out Each bit gate select clock in out gate
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Transfer of data Register operation: Detailed operation A A BUS Registers are sets of bits that are gated together. The lines shown are sets of connecting lines, one for each bit. Register transfer occurs when bits from one register are gated onto a bus, and the bus is gated into another register. The transfer itself is synchronized by a clock pulse
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ALU operations ALU AX DX Registers immediately available to the ALU - example: ADD AX, DX result clock Set up Transfer edge
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Schematic Design The simplest model Control Unit ALU Memory I/O Communications Bus
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Schematic Design The simplest model Control Unit ALU Memory I/O Communications Bus Decoded addresses activate addressed memory element Selected address activates Addressed interface address data
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Control unit 2 Very Basic Design MAR MDR ACCUMULATOR IR PC Instruction decoder System clock REGISTERS Address bus
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Memory Interface The MAR and MDR are the interface between the CPU and the memory MAR MDR select MEMORY
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Bytes and words Memory is organized in addressable units Normally, an addressable unit is a byte (8 bits) Computers usually work with larger units, typically words. These may be 2, 4, or 8 bytes (16, 32, or 64 bits)
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Instructions The simplest format The OP CODE is the code of the
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SOEN_228-11_week5_slides - SOEN 228/4 2011 T. Fancott Week5...

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