SOEN_228-11w_week10memory

SOEN_228-11w_week10memory - SOEN 228/4 2011 Week 10 Memory...

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SOEN 228/4 – 2011 Week 10 Memory Architecture
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Technology-types of memory DRAM Dynamic RAM needs to be refreshed at regular intervals. SRAM Static RAM- does not need to be refreshed. Faster, more expensive and less dense than DRAM. Erased on power off. ROM Read only memory. Contents “ burned in” by manufacturer (good for boot programs, BIOS, constants). PROM programmable ROM can be programmed on site by designers. Flash memory EPROM (erasable PROM) Persistent memory that can be erased and reprogrammed (keys, ipods)
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Memory Hierarchy CACHE MAIN MEMORY Secondary Memory registers
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Memory Hierarchy Typical Hierarchy: Level Name Technology Access time Cost/bit 0 Cache semiconductor 1 clock ~ 10 4 1 RAM semiconductor 5 ~10 clocks ~ 10 3 2 Disk optical/magnetic 10 4 clocks 1 Latency: access time Locality location of addressed item Locality of reference : Principle whereby programs and data are usually clustered in local areas
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Hierarchy depends on locality of reference Programs tend to spend most of their time in small areas of memory (loops, subroutines) Data used tends to be in local areas Memory hierarchy maps areas that are in current use into faster media (cache), (Virtual memory) Mapping is handled by the o/s, not by the programmer
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Structure of a typical RAM chip Interface of a 4M x 4 bit RAM chip Address bits required to identify the 4M (=2 22 ) locations: 22 bits [= log2 4M = log2 #memory locations ] Data bits in each location: 4 bits [= # data bits in each location of the RAM chip] Control bits : read/write (0 for read, 1 for write). Chip select 1 implies the chip is enabled.
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Chip Layout
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Typical write operation Write 1010 2 into [123456h] This can be performed with the following interface signals: A21 …. .A0 = 123456h D3 …D0 = 0101 2 R/W = 1 CS = 1
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Interface variations Signals can be time multiplexed to reduce the number of pins Example: Address could be multiplexed into 2 successive 11 bit signals Speed: Dram is often slower than the CPU (up to 5 clock cycles)
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Design procedure Specify width of path: Example, 16 bits Each chip has a 4 bit data path-we need 4 chips cs r/w We now have a 4 meg by 16 bit memory
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Design procedure-2 Specify number of 16 bit words Example, 16 x 8 meg Each chip has a 4 bit data path-we need 4 chips cs r/w We now have an 8 meg by 16 bit memory r/w
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Design-3 Note we need 22 bits to select 4 meg, and 23 bits to select 8 meg. The extra bit selects the lower bank with bit 23 = 0, and the upper bank with bit 23 = 1 The 16 bits of output from the 2 banks need to be joined together
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Final Memory design using 8 chips
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Memory Interface - write MAR Memory Address Register contains the address involved in the current memory operation. MDR
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SOEN_228-11w_week10memory - SOEN 228/4 2011 Week 10 Memory...

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