SOEN228_11w_week_11_IO_intro

SOEN228_11w_week_11_IO_intro - SOEN228/4 Week 10 intro to...

Info iconThis preview shows pages 1–12. Sign up to view the full content.

View Full Document Right Arrow Icon
SOEN228/4 Week 10 intro to I/O Refer to chapter 12, Rajaraman, Radhakrishnan
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Bus Design Basic I/O: Program controlled directly from the CPU to the I/O interface This technique was used in early designs that did not support multiprogramming, including the original microcomputers ( Intel 8008, 8080, etc.)
Background image of page 2
Original System Bus How do the computer components communicate in early designs? Answer: via the System Bus. The bus: external (to the CPU) means of communication between the CPU and other computer components. NOTE: there is also an internal bus within the CPU that connects its registers, ALU and Control Unit –do NOT confuse it with the System Bus.
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Original System Bus details The system Bus can often be seen as three “sub- busses”: –Data Bus. Primarily for data-only communication among different types of units, such as CPU, Memory, and I/O devices. –Address Bus. Used to communicate address information, i.e. where to look for/to send to the data (an address in the memory; I/O device number). –Control Bus. Control data lines to report status, to request writing or reading between communicating parties.
Background image of page 4
The System Bus Bus architecture DATA ADDRESS CONTROL CPU MEMORY I/O
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
The System Bus The concept of a system bus is to provide addressing capability to access all units of the computer. The data bus carries the data between the CPU and the unit addressed (memory, I/O) The control bus carries the timing signals (clock) and the signals that enable the transfer (read/write, data ready,etc.) Note: modern systems have more than one bus.
Background image of page 6
Bus Design The first generations of microcomputers had one bus that operated at the speed of the processor. Memory and I/O operated at the speed of the processor, and synchronization with slow devices was handled through interface design. (ready bit, interrupts) A bus has 3 categories of signal: Address Data Control I/O devices can be handled through memory mapping or through a dedicated address bus
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Control Lines Typical set: Standard controls Clock R/W I/O ready Interrupt request (IRQ) DMA controls Request Grant Select Lock
Background image of page 8
Basic Principle Computer integrated circuits (ic’s) operate with only with other ic’s. They share similar characteristics (speed, voltage). A cpu can only read and write to a bus, with an address and data. An I/O interface must therefore look like memory to a CPU
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Basic interface design Control and data transfer is handled through interface registers, each of which has an address, and each address can behave like a memory location control status Data in Data out
Background image of page 10
Each register has an address. The cpu accesses the control register with one address, and the data register with the following address. Often the control and status registers share
Background image of page 11

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 12
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 06/30/2011 for the course SOEN 228 taught by Professor T.fancott during the Winter '11 term at Concordia Canada.

Page1 / 57

SOEN228_11w_week_11_IO_intro - SOEN228/4 Week 10 intro to...

This preview shows document pages 1 - 12. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online