SOEN228_11w4_week_6RTL_intro_to_assy

SOEN228_11w4_week_6RTL_intro_to_assy - SOEN 228 Week6-2...

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SOEN 228 Week6-2
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Intel Architectures 8088 architecture 16 bit, 1 M addressing with segments AH AL BH BL CH CL DH DL DI SI SP BP DS ES CS SS AX BX CX DX DATA SEGMENT EXTRA SEGMENT CODE SEGMENT STACK SEGMENT Destination Index Source index Stack pointer Base pointer FLAGS IP
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Intel Architectures x86 architectures, 32 bit AH AL BH BL CH CL DH DL DI SI SP BP DS ES CS SS AX BX CX DX DATA SEGMENT EXTRA SEGMENT CODE SEGMENT STACK SEGMENT Destination Source index Stack pointer Base pointer EFLAGS EIP FS GS
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CPU model Very simplified x86 MAR MDR IP IR DH DL CH CL Instruction decoder System clock REGISTERS(16 bit) Address bus BH BL AH AL FLAGS AX BX CX DX Address logic
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Flags Flag register: Condition codes Condition codes record details of the results of an operation C P Z S T I D O C: carry P: parity Z: zero S: sign T: trap I: interrupt D: direction O: overflow
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Condition codes Results of an operation: examples An add results in a zero: z is set to 1 A subtract results in a negative number: s is set to 1 The zero flag is set when the result of an operation is zero Overflow is set when the result is too large to fit in the operand it originally occupied
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Some instructions MOV destination, source mov ax, bx ADD destination, source add ax, bx CMP destination, source cmp ax, cx DEC destination dec cx INC destination inc ax JMP LABEL jmp next LOOP LABEL loop top SUB destination, source sub ax, bx
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Definitions Destination: where the result is stored. It may be a register or a memory address It may be 8 bits or 16 bits in our simplified machine Source: the other operand It may be a register or a memory address as above LABEL: a name given to a line of code, which is interpreted as the address of that line
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Instruction details MOV Operates register to register Or memory to register Or register to memory NOT memory to memory The register size determines the operand size MOV AX, VAL1 ; AX VAL1
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Instruction details ADD (same address restrictions as MOV) Result in destination, flags (z,s,o) SUB (ditto) CMP( same address restrictions as MOV) Result in flags(z,s) DEC (one address only, result in destination, flags(z,s)) INC (as above) JMP LABEL: go to address “label” LOOP LABEL: decrement CX, test it for zero, go to address “label” until CX = 0 (CX is treated as an unsigned counter)
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Register Transfer Language (RTL) MOV AX, VAL1 MAR IR:ADDR MDR VAL1 AX MDR MOV AX, BX AX BX MOV VAL2, DX MAR IR:ADDR MDR DX VAL2 MDR
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MORE RTL ADD AX, DX AX AX + DX FLAGS values of z,s,o produced by ALU SUB AX, DX AX AX - DX FLAGS values of z,s,o produced by ALU HOW MANY CLOCK PULSES
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More precise RTL ADD AX, DX ALU AX ,ALU DX, AX ALU(add) FLAGS ALU (z or s or o) SUB AX, DX ALU AX ,ALU DX, AX ALU(add) FLAGS ALU (z or s or o)
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ALU operations ALU AX DX Registers immediately available to the ALU - example: ADD AX, DX result clock Set up Transfer edge FLAGS
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Simplified model of Intel Architecture
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Microprogrammed control unit An internal memory holds the set of signals that control Register transfers
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