SOEN228_Architecture_wk_12

SOEN228_Architecture_wk_12 - SOEN228 week 12 System...

Info iconThis preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
SOEN228 week 12 System architecture CPU Architecture Ref: Randall Hyde http://www.coinfo.cefetpb.edu.br/professor/ilton/apostilas/art/Volume %202/CPU%20Architecture.pdf
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Speeding up the CPU – Technological evolution A hardwired, or random logic , approach uses decoders, latches, counters, and other logic devices to move data around and operate on that data. The microcode approach uses a CPU opcode as an index into a table of operations ( micro-instructions )and executes a sequence of them to perform a CPU instruction. Random logic can implement the sequence without the fetch-execute time that a memory, even a fast memory, implies. The drawback to random logic is that it is difficult to design CPUs with large and complex instruction sets using a random logic approach.
Background image of page 2
Intel approach Most modern (non-x86) processors use random logic. The 80x86 family uses a combination of these technologies to improve performance while maintaining compatibility with the complex instruction set that relied on microcode way back in 1978.
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Optimizing fetch Wide instruction path Randall Hyde, 4.8.1 Example MOV fetch on 32 bit architecture (32 bit data bus) If the MOV instruction fetches an eight-bit displacement from memory, the CPU will also fetch the following three bytes following the displacement (the 32-bit data bus fetches four bytes in a single bus cycle). The second of these three bytes is the opcode of the next instruction. This means that the control unit can decode the next instruction while the current instruction is executing. This overlaps a portion of the MOV instruction with the beginning of the execution of the next instruction.
Background image of page 4
Use of bus idle cycles Randall Hyde, 4.8.1 During the execution of this MOV instruction the CPU is not accessing memory. (while storing the data into the destination register the bus is idle). During this time period the CPU can pre-fetch instructions and save them for the next execution. The hardware to do this is the prefetch queue. The next slide shows the internal organization of a CPU with a prefetch queue. The Bus Interface Unit is responsible for controlling access to the address and data busses. Whenever some component inside the CPU wishes to access main memory, it sends this request to the bus interface unit (or BIU)that handles simultaneous requests for bus access by different modules (e.g.,the execution unit and the prefetch queue).
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Bus Interface Unit To optimize instruction and data fetch, modern computers use a Bus Interface Unit that controls all access to the address and data
Background image of page 6
Image of page 7
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 06/30/2011 for the course SOEN 228 taught by Professor T.fancott during the Winter '11 term at Concordia Canada.

Page1 / 38

SOEN228_Architecture_wk_12 - SOEN228 week 12 System...

This preview shows document pages 1 - 7. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online