SOEN228-11w4_sequential_circuits

SOEN228-11w4_sequential_circuits - ONE BIT(0 OR 1(0 VOLTS...

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SOEN228w-11 Week4 Sequential circuits, registers, counters With extracts from Morris Mano 2002
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Sequential circuit model
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Propagation delay in a gate
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Basic latch design
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Q =R’(S+q)
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K map 0 1 0 0 1 1 0 0 q R S 00 01 11 10 0 1 Present state Next State Q
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JK Q = R’(S+q) R’ = q’ +K’ S = Jq’+ q Q = C(q’ + K’)(Jq’ +q) = C(Jq’+ K’q+JK’q’) Q = C(Jq’ +K’q} 0 0 1 1 1 0 0 1 JK q 00 01 11 10 0 1
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JK
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Storage The basic element DATA DATA SELECT select R/W R/W
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Unformatted text preview: ONE BIT(0 OR 1), (0 VOLTS OR 5 VOLTS) ONE BYTE: 8 BITS ADDRESSED AS ONE UNIT Addressing • Decoder Decoder Binary in e.g. 101 Selector wires out line 5 for 101 Selector Selector Binary in Selected address recognized USED TO ADDRESS MEMORY ELEMENTS USED TO ADDRESS I/O INTERFACES Concept of a bus • Tri-state buffers • • 1 • off...
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This note was uploaded on 06/30/2011 for the course SOEN 228 taught by Professor T.fancott during the Winter '11 term at Concordia Canada.

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SOEN228-11w4_sequential_circuits - ONE BIT(0 OR 1(0 VOLTS...

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