SOEN228w11_advanced_Bus_structures

SOEN228w11_advanced_ - SOEN228/4 Week 11 Advanced Bus Structures Bus master The bus master controls all bus transfers All bus locations have an

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SOEN228/4 Week 11 Advanced Bus Structures
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Bus master The bus master controls all bus transfers All bus locations have an address The master reads from one address and writes to another Slave units can request service through one or more control lines
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Bus masters A bus master controls the bus and transfers data from one unit to another The CPU is a master, reading and writing memory, and transferring data to interfaces The DMA is also a bus master, stealing bus cycles to write directly from a disk interface to main memory
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Multiple bus masters A bus may have more than one master Example DMA (direct memory access) DMA can “steal” bus cycles to transfer data directly from a peripheral interface to memory Other units can also use this technique to transfer to memory or to other units. This may also be called “burst mode” Dual processors can cooperate by using the same memory they need a protocol that allows them to share The protocol usually provides one or more lines to request and control the bus The bus may also be locked to achieve an “atomic” operation, such as read- modify-write Atomic: operation that is done as a single, indivisible, sequence
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View of multiple busses First we look at how the architecture developed, from the early days of a single bus, to a network of busses.
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Evolution of PC bus design Original PC bus: 16 bits address, 16 bits data, 4.77 MHz. It became known as the ISA bus. All original I/O cards were designed for this bus. Many still use it. Compatibility with a large number of hardware products Few hardware peripherals fully utilize the speed of newer buses. (apart from video devices) As the cpu speed increased, it became necessary to differentiate between the memory bus and the I/O bus. The memory bus became known as the local bus
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System bus (local bus) Typical local bus frequencies: 66 MHz, 100 MHz, 133 MHz, 400 MHz, 1GHz Only memory and a few selected peripherals (e.g., the PCI Bus Controller) sit on the CPU s bus and operate at this high frequency.
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This note was uploaded on 06/30/2011 for the course SOEN 228 taught by Professor T.fancott during the Winter '11 term at Concordia Canada.

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SOEN228w11_advanced_ - SOEN228/4 Week 11 Advanced Bus Structures Bus master The bus master controls all bus transfers All bus locations have an

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