week_8_intro_to_architecture

week_8_intro_to_architecture - SOEN 228 Week 8 Introduction...

Info iconThis preview shows pages 1–15. Sign up to view the full content.

View Full Document Right Arrow Icon
SOEN 228 Week 8 Introduction to Architecture
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
The CPU Generic CPU illustration BUS BUS INTERFACE PC IR R1 R2 ALU CONTROL UNIT MEMORY I/O Internal busses CPU registers
Background image of page 2
RTL The Bus Interface in a simple model consists of : MAR Memory Address Register MDR Memory Data Register The CPU Registers have special functions and general functions Typical Special: PC, IR, SP, Index General: Fast storage immediately accessible to the control unit and the ALU RTL (Register Transfer Language): a notation for expressing the movement of data and operations on it. In a CPU, it defines the microprograms that implement machine instructions
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
General Principles Refer to Chapter 9 in the text Design of Instructions Elements: Op code defines the operation Address: The address of the operand OP ADDRESS
Background image of page 4
Design considerations In principle, 8 bits can define 256 operations N address bits can access 2 N addresses Trade-offs Length of instruction, ways of accessing data (memory, registers, I/O) Options: variable length op codes, variable length instructions, bit allocations for addressing modes, multiple address references (register , register: register memory; immediate operand, indirect addressing)
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Classic solutions Assign bits for addressing modes No modes Bits for modes Problem: Reduced space for address Solution: Full range provided by Register indirect, default – PC relative OP Address I N R M Address
Background image of page 6
Historical solutions IBM 370 16 general purpose registers opc R R opc R R opc opc opc R R R R R I R L R disp disp disp disp disp
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Addressing modes Base Segment PC relative Indirect Direct Immediate
Background image of page 8
Intel Architectures Not covered in text book 8088 architecture 16 bit, 1 M addressing with segments AH AL BH BL CH CL DH DL DI SI SP BP DS ES CS SS AX BX CX DX DATA SEGMENT EXTRA SEGMENT CODE SEGMENT STACK SEGMENT Destination Index Source index Stack pointer Base pointer FLAGS IP
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Intel Architectures x86 architectures, 32 bit AH AL BH BL CH CL DH DL DI SI SP BP DS ES CS SS AX BX CX DX DATA SEGMENT EXTRA SEGMENT CODE SEGMENT STACK SEGMENT Destination Source index Stack pointer Base pointer EFLAGS EIP FS GS
Background image of page 10
Intel CPU model Very simplified x86 MAR MDR IP IR DH DL CH CL Instruction decoder System clock REGISTERS(16 bit) Address bus BH BL AH AL FLAGS AX BX CX DX Address logic
Background image of page 11

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Flags Flag register: Condition codes Condition codes record details of the results of an operation C P Z S T I D O C: carry P: parity Z: zero S: sign T: trap I: interrupt D: direction O: overflow
Background image of page 12
Condition codes Results of an operation: examples An add results in a zero: z is set to 1 A subtract results in a negative number: s is set to 1 The zero flag is set when the result of an operation is zero Overflow is set when the result is too large to fit in the operand it originally occupied
Background image of page 13

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Architecture
Background image of page 14
Image of page 15
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 43

week_8_intro_to_architecture - SOEN 228 Week 8 Introduction...

This preview shows document pages 1 - 15. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online