276202 - designfeature By Michael Crews and Yong...

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www.edn.com February 20, 2003 | edn 65 A SIMPLE CIRCUIT ADDRESSES THE ERRORS AND LIMITATIONS OF ASYNCHRONOUS DESIGN. W ith the increasing integration of multi- ple systems on single SOCs (systems on chip) or boards, multiple clock frequencies in sin- gle digital designs have become common. Because of the asynchronous nature of these designs,passing data or control signals between logic operating on different clock frequencies presents a special set of problems. Because asynchronous design is unfamil- iar to most experienced digital designers, errors are common. Many of these errors find their way into the silicon and even into production because they are nearly impossible to detect in simulation and easily missed in postsilicon validation. Problems of performance degradation, back-end EDA-tool in- compatibility, and dependency on the frequency re- lationship of the clocks involved often plague even functionally correct implementations. Frequency dependency is problematic for production tests that run the parts at different speeds, and it limits reusability in future designs with different system frequencies. You can address all of these errors and limitations with a fairly simple circuit that works for both data and control logic. The circuit requires both signal synchronization and a handshake protocol ( Figure 1 ). The synchro- nizer guarantees the amount of time required for the signal level to settle following a metastability viola- tion, thereby preventing undetermined signal levels from propagating to the destination module. The handshake protocol maintains signals levels long enough to ensure that the system does not miss sig- nal events or wrongly interpret them as multiple events. Normally, the circuit synchronizes only handshake signals, which signify the validity of data being transferred to the destination clock domain. Once the handshake signals transfer to the destina- tion-clock domain,the system clocks the data set di- rectly to the destination module.The most common mistakes in this situation involve the handshake sys- tem and its usage. SYNCHRONIZATION A signal that a system sends from one clock do- main arrives as an asynchronous signal in the desti- nation-clock domain, possibly violating the desti- nation flip-flop setup or hold time, causing it to enter a metastable condition.This condition,in turn, causes propagation of nonbinary signals to other parts of the system. The time required for the metastable flip-flop to settle out to a binary voltage level varies. A double-stage synchronizer ( Figure 2 ) is the most widely used method of stabilizing a sig- nal in the destination-clock domain. If the first flip- flop stage enters the metastable condition, it has a full clock period to stabilize before the second flip- flop stage samples it. Only the second-stage value is propagated to other parts of the system. To ensure that interconnect delay does not reduce the one- clock-period settling time that the double-stage syn- chronizer supplies,you must minimize interconnect
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276202 - designfeature By Michael Crews and Yong...

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