EEIOL_2007DEC24_EDA_TA_01 - 1 EE Times-India | December...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 1 EE Times-India | December 2007 | By Saurabh Verma Engineering Manager Atrenta Ashima S. Dabare Consulting Applications Engineer Atrenta Introduction SoCs are becoming more com- plex these days. A lot of func- tionality is being added to chips and data is frequently transferred from one clock domain to anoth- er. Hence, clock domain crossing verification has become one of the major verification challenges in deep submicron designs. A clock domain crossing occurs whenever data is trans- ferred from a flop driven by one clock to a flop driven by another clock. In Figure 1, signal A is launched by the C1 clock do- main and needs to be captured properly by the C2 clock domain. Depending on the relationship between the two clocks, there could be different types of prob- lems in transferring data from the source clock to the destina- tion clock. Along with that, the solutions to those problems can also be different. Traditional methods like simulation and static timing analysis alone are not sufficient to verify that the data is trans- ferred consistently and reliably across clock domains. Hence, new verification methodologies are required, but before devising a new methodology it is impor- tant to understand the issues re- lated to clock domain crossings properly. Different types of clock domain crossings are discussed here along with the possible is- sues encountered in each one of them and their solutions. A new verification methodology is then proposed which will ensure that data is transferred correctly across clock domains. In all the subsequent sec- tions, the signal names shown in Figure 1 are directly used. For example, C1 and C2 imply the source and destination clocks re- spectively. Similarly A and B are used as source and destination flop outputs respectively. Also, the source and destination flops are assumed to be positive edge triggered. Clock Domain Crossing Issues This section describes three main issues, which can possibly occur whenever there is a clock do- main crossing. The solutions for those issues are also described. A. Metastability Problem. If the transition on sig- nal A happens very close to the active edge of clock C2, it could lead to setup or hold violation at the destination flop “FB”. As a re- sult, the output signal B may os- cillate for an indefinite amount of time. Thus the output is unstable and may or may not settle down to some stable value before the next clock edge of C2 arrives. This phenomenon is known as meta- stability and the flop “FB” is said to have entered a metastable state. Metastability in turn can have the following consequences from a design perspective: 1. If the unstable data is fed to several other places in the design, it may lead to a high current flow and even chip burnout in the worst case....
View Full Document

This document was uploaded on 07/12/2011.

Page1 / 7

EEIOL_2007DEC24_EDA_TA_01 - 1 EE Times-India | December...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online