EEL4712_midterm1_sp10

EEL4712_midterm1_sp1 - EEL 4712 Name Midterm 1 – Spring 2010 VERSION 1 UFID COVER SHEET Problem Points 1(8 points 2 8 points 3(16 points 4(16

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Unformatted text preview: EEL 4712 Name: Midterm 1 – Spring 2010 VERSION 1 UFID: COVER SHEET: Problem#: Points 1 (8 points) 2 ( 8 points) 3 (16 points) 4 (16 points) 5 (16 points) 6 (16 points) 7 (16 points) 8 (8 points) IMPORTANT: • Please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed wrong. • As always, the best answer gets the most points. Total: Regrade Info: ENTITY _entity_name IS PORT(__input_name, __input_name : IN STD_LOGIC; __input_vector_name : IN STD_LOGIC_VECTOR(__high downto __low); __bidir_name, __bidir_name : INOUT STD_LOGIC; __output_name, __output_name : OUT STD_LOGIC); END __entity_name; ARCHITECTURE a OF __entity_name IS SIGNAL __signal_name : STD_LOGIC; BEGIN -- Process Statement -- Concurrent Signal Assignment -- Conditional Signal Assignment -- Selected Signal Assignment -- Component Instantiation Statement END a; __instance_name: __component_name PORT MAP (__component_port => __connect_port, __component_port => __connect_port); WITH __expression SELECT __signal <= __expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN __constant_value; __signal <= __expression WHEN __boolean_expression ELSE __expression WHEN __boolean_expression ELSE __expression; IF __expression THEN __statement; __statement; ELSIF __expression THEN __statement; __statement; ELSE __statement; __statement; END IF; CASE __expression IS WHEN __constant_value => __statement; __statement; WHEN __constant_value => __statement; __statement; WHEN OTHERS => __statement; __statement; END CASE ; <generate_label>: FOR <loop_id> IN <range> GENERATE-- Concurrent Statement(s) END GENERATE; 1) (8 points) For the entity given below, explain how the generic WIDTH gets its value: library ieee; use ieee.std_logic_1164.all; entity ALU is generic ( WIDTH : positive := 16); port ( input1, input2 : in std_logic_vector(WIDTH-1 downto 0); sel : in std_logic_vector(3 downto 0); output : out std_logic_vector(WIDTH-1 downto 0)); end ALU; 2) (8 points) Describe the violation of the synthesis guidelines for combinational logic in the following example: library ieee; use ieee.std_logic_1164.all; entity MUX is port ( input1, input2 : in std_logic_vector(15 downto 0); sel : in std_logic; en : in std_logic; output : out std_logic_vector(15 downto 0)); end MUX; architecture BHV of MUX is begin -- BHV process(input1, input2, sel) begin if en = '1' then output <= (others => '0'); elsif sel = '0' then output <= input1; else sel = '1' then output <= input2; end if; end process; end BHV; 3) A. (8 points) For the following code, fill in the waveform for “output” assuming the values shown are in decimal format: entity ADD is port ( input1, input2 : in std_logic_vector(15 downto 0); output : out std_logic_vector(15 downto 0); overflow : out std_logic); end ADD; architecture BHV of ADD is signal temp : unsigned(16 downto 0); begin process(input1, input2) begin temp <= unsigned("0"&input1) + unsigned("0"&input2);...
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EEL4712_midterm1_sp1 - EEL 4712 Name Midterm 1 – Spring 2010 VERSION 1 UFID COVER SHEET Problem Points 1(8 points 2 8 points 3(16 points 4(16

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