EEL4712_midterm2_sp10_solution

EEL4712_midterm2_sp10_solution - EEL 4712 Name: “(a /(4...

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Unformatted text preview: EEL 4712 Name: “(a /(4 lL/“le Midterm 2 — Spring 2010 VERSION 1 UFID: Sign your name here if you would like for your test to be returned in class: IMPORTANT: - Please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed wrong. - As always, the best answer gets the most points. COVER SHEET: Problem#: 1 (6 points) 2 (6 points) Total: 3 (8 points) 4 (10 points) 5 (12 points) 6 (6 points) 7 (6 points) 8 (12 points) 9 (30 points) 10 (4 points) Regrade Info: ENTITY _entity_name IS PORT(_input_name, _input_name : IN STD_LOG|C; _input_vector_name : IN STD_LOGIC_VECTOR(_high downto _low); _bidir_name, _bidir_name : INOUT STD_LOG|C; _output_name. _output_name : OUT STD_LOGIC); END _entity_name; ARCHITECTURE a OF _entity__name IS SIGNAL _signal_name : STD_LOG|C; BEGIN -- Process Statement -- Concurrent Signal Assignment -- Conditional Signal Assignment -- Selected Signal Assignment -- Component Instantiation Statement END a; _instance_name: _component_name PORT MAP (__component_port => _connect_port, _component_port => _connect_port); WITH _expression SELECT _signal <= _expression WHEN _constant_value, _expression WHEN _constant_value, _expression WHEN _constant_va|ue, _expression WHEN _constant_va|ue; _signal <= _expression WHEN _boolean_expression ELSE _expression WHEN _boolean_expression ELSE _expression; IF _expression THEN _statement; _statement; ELSIF _expression THEN _statement; _statement; ELSE _statement; _statement; END IF; CASE _expression IS WHEN _constant_va|ue => _statement; _statement; WHEN _constant_value => _statement; _statement; WHEN OTHERS => _statement; _statement; END CASE; <generate_label>: FOR <|oop_id> IN <range> GENERATE -- Concurrent Statement(s) END GENERATE; type _identifier is type_definition; subtype _identifier is 5ubtype_indicati0n; 1) (6 points) For the memory entity given below, which of the answers best describes the memory structure that is inferred during synthesis? library ieee; use ieee.std_logic_ll64.all; use ieee.std_logic_unsigned.all; entity ram is port (clk : in std_logic; we : in std_logic; addrl : in std_logic_vector(4 downto 0); ader : in std_logic_vector(4 downto O); data_in : in std_logic_vector(3 downto O); read_datal : out std_logic_vector(3 downto O); read_data2 : out std_logic_vector(3 downto 0)); end ram; architecture syn of ram is type ram_type is array (31 downto O) of std_logic_vector (3 downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(addrl)) <= di; end if; end if; end process; I read_datal <= RAM(conv_integer(addrl)); read_data2 <= RAM(conv_integer(addr2)) end syn; a) Single-port memory, synchronous writes, synchronous reads b) Dual-port memory, synchronous writes, synchronous reads GD Dual-port memory, synchronous writes, asynchronous reads d) Dual-port memory, asynchronous writes, asynchronous reads 2) (6 points) What is the minimum number of adders and multipliers that are needed to create a datapath for the following pseudo-code, assuming that an appropriate controller exists? for (i=0; i < 100; i++) ( result = a[i]*b[i]*c[i]*d[i] + e[i]*l6 + f[i]*8 + result; l / Miler / mn/le/z'er J 3) a. (2 points) Write a VHDL type declaration called MY_ARRAY that creates a 2D array with 8 rows and 4 columns, where each element is a 32—bit std_logic_vector. ty/e M‘LMKAY ’5 may (0472710 in 3) at 5H.//oy’c,v€67€r [BU/own 0); b. (2 points) Write a VHDL type declaration called MY_ARRAY that creates a 2D array with unconstrained ranges for each dimension, where each element is a 32-bit std_logic_vector. We #11.er is ant/(new WWW/q! Wont Al/aflzmlwlsumo a) c. (2 points) Using the type from part b, instantiate an object of type MY_ARRAY with 50 rows and 100 columns. WM, {1.3: ,WLAM/n’fo +7 9?) 0+0 97); d. (2 points) What doesn’t VHDL allow in the following type declaration? type MY_ARRAY is array (natural range<>, natural range<>) of std_logic_vector WW, Joey/H QHOW Waml'mirtpa‘ affliyj 5+ an unansl‘rmqpl 47/5 4) a. (5 points) Briefly explain the purpose of the horizon sync (h_sync) and vertical sync (v_sync) signals in the VGA lab. Mm SyflL/i pm;ng 7%? mid ML 646% fox/V 01‘ Wye/5 VJyfic Syfléhféfl/z€5 Hie fit/wk oWLHIe— emf/ha JC/Fen 6/26. H fameyf/zg WWW +0 i631?! f5 rim/rill} q+l’/L2 791/ 4147‘) b. (5 pointsh}Nhy are the color signals turned off at certain times during the drawing of the screen? When does this occuryA/hat is the name of these intervals where the color is off? a) +7 Cit/nip? 430114437} v/m/e e/c’c/mn /€4m [5 16/14} Mll/é/ ’13 4’7” 85/;6 of {Wm Hie éotlmz 07L 1% 504a,” éqC/C ,5 HQ 7%/' A) Man/({4} {Him/M5 5) (12 points) Fill in the code provided below to create a series of delay registers with generic width and number of delay cycles. You must use a structural architecture with the provided generate loop that connects together the register (reg) components. The circuit should look like this: output Reg . . . . . . . . . . input MHDTH NUM_CYCLE$ library IEEE; use IEEE.STD_LOGIC_1164.all; entity delay is generic(num_cycles : positive; width : positive); port( clk : in std_logic; rst : in std_logic; input : in std_logic_vector(width-l downto 0); output : out std_logic_vector(width-l downto 0)); end delay; architecture str of delay is type ARRAY_TYPE is array (0 to num_cycles) of std_logic_vector(width—1 downto 0); component reg generic (width : positive := 32); port(clk : in std_logic; rst : in std_logic; input : in std_logic_vector(width—l downto 0); output : out std_logic_vector(width—l downto 0)); end component; signal reg_val : ARRAY‘TYPE; begin high/01(0) 13mm; U_DELAY : for i in O to num_cycles—l generate U_REG : reg generic map (width => width) port map (clk => clk, rst => rst, (mi :7 mj,ya/[;)/ dub/mi ’7 Ayn/4M flv) ); end generate U_DELAY; Ouiflut Z 5‘ wag/(with) end str; 6) (6 points) Map the following circuit onto 3-input, 2—output LUTs by drawing shapes around each portion of the circuit that is mapped to an individual LUT. 7) (6 points) What is the maximum number of gates that can be implemented in a 3-input, 2- output LUT? no Mai/(Mam 8) (12 points) Briefly describe the components in an FPGA used for reconfigurable interconnect. Fault/t7 lm/(j ’ WW7 56%“ eve/7 my 0M1 Mm” ” 11 [MJ cow/reciebn 50x ‘ C0M€67Lj (M f/o +0 rout/4; frqc/U 5 Witch box ~ [MI/ml; "daffy flaw/U byef/W/ 9) A. (12 points) For the following pseudo-code, create a datapath that is capable of performing all necessary behavior. Clearly show all inputs/outputs, multipliers, subtractors, comparators, registers, muxes, wires, and control signals. n = input; - result = 1; while (n > 0) { result = result*n; output = result; B. (12 points) For the datapath in the previous problem, draw an FSM capable of controlling the datapath to perform the illustrated code. In the circle for each state of the FSM, show the statements from the code that are performed in that state. C. (6 points) For each state in your FSM, list the values of the control signals that configure the datapath to perform the appropriate operations. Assume that the left input to a mux uses a select value of ’1’. Specify default control values to avoid having to list every control signal for each state. OWL/q ll../&p :/ L/l (Mag/l ; 10) (4 free points) Who will replace Tebow as the starting QB for the football team next year? ...
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EEL4712_midterm2_sp10_solution - EEL 4712 Name: “(a /(4...

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