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EEL4712T1Fall09Solution - 7 2 EEL 4712 — Digital Design W...

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Unformatted text preview: 7%, 2 , , EEL 4712 — Digital Design W Test 1 — Fall Semester 2009 Problem 1 Name MM“ 1. VHDL Analysis (timing diagrams): Given the following VHDL specification, complete the following timing diagram for outputs 2(0), 2(1), 2(2), 2(3). 16 pts. - LlBRARY ieee; USE ieee.std_logic_1164.all ; IMPORTANT: ENTITY Prob‘i IS Throughout this test, _ — PORT( D, CLOCK, CLR1, CLR2 : lN STD_LOGlC; p'ease be neat and Will?“ 2 :OUT STD__LOGlC_VECTOR(O TO 3)); (WWW) GaierUY- ”we END Prom ; flL/e/ cannot read It WIth a reasonable effort, it is lagngECTURE PiArCh OF Probl IS .3 9 62 _ Z70) assumed to be wrong. PROCESS (CLOCK, CLR1) C «if? M“ BEGIN .. IF CLR1 = '0' THEN 2(0) <= '0'; 54’9“ ELSIF CLOCK'EVENT AND CLOCK='1 THEN IF CLR2 = '0' THEN 2(0) <= '0'; - ELSE 2(0) <= D; D‘— W I END IF; END IF; y fifld/‘f END PROCESS; PROCESS (D,CLOCK) BEGIN IF CLOCK='1' THEN 2(1) <= D; 'mP0”3“t_N°te= . END IF; 0 Every fle-flOp and latch starts off WIth END PROCESS; an unknown value. PROCESS (D, CLOCK) o Please show propagation delays. BEGIN IF CLOCK='1' THEN Z(2) <= D; ELSE 2(2) <= ‘0’, END IF; 9 f , 57} (2;) END PROCESS; 1% \ W PROCESS (CLOCK) 766 !' ,, ‘ BEGIN CAM! ( L_:'_____J IF CLOCK'EVENT AND CLOCK='1' THEN 2(3) <= D; .7 ( END IF; »- ; END PROCESS; J) P <54 7% 3) END P1ArCh; C deH/i wig 100.0h8' '- 3 i EEL 4712 — Digital Design Test 1 — Fall Semester 2009 Problem 2 Name 2(a). Using the GENERIC feature of VHDL, complete the following code that will define a “generic” component named nBitAdd shown below; The generic component is a n-bit, ripple—carry adder containing “n” full adders. W’é nBitAdd Equations for a full adder: 8 <= A XOR B XOR Cin; Cout <= (A AND B) OR ((A OR B) AND Cin); LIBRARY ieee; USE ieee.std_logic__1164.all; USE ieee. std _l_ogic unsignedall; nBitAdd IS - ENTITYgg/yg/Q M (m ”147464 :34) KW?“ (’4 3313/ 4/} 344/4244 [444/4343 Cm J4 534-4444” , 4W2”? 446/4: 1/42/7474 3 3444333 3/3 / @245 447 3/7 444/5) END nBitAdd; ARCHITECTURE genericAdder OF nBitAdd IS ’ . 1 ? \ SIGNAL 3 .677 {74243444474 4&5??? (43 9444434474 42>, , -—344/ 33737 BEGIN , PROCESS( 34) 5/ Cm ) -- Hint: Use FOR loop; 4444/ 4744 3:43;; PM? I) 1344 73 42 w; 44W" 3434- 443 3/44 44-3 X44 474/) 47/4/34 (44 3/43 44 33 43 ((4/4 344 4033/34} (7/43)); 44} 344/”) ”444745 47/4135 END PROCESS; END genericAdder; #2. EEL 4712 — Digital Design Test 1 — Fall Semester 2009 Name 2(b). Given the following ENTITY definition, give me the PORT MAP statement that will create a 32—bit'adder using the above generic adder. ENTITY TestGenAdd Is PORT( cm : IN STD_LOGlC; 4 x, y: IN STD_LOGlC;VECTOR(31 DOWNTO 0); - - Cout: OUT STD_LOGlC; sumOut: OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END TestGenAdd; Put the PORT MAP statement here: M32 Jag/2W4?” éE/Vffi/c’ Mflflflwz .2: )23) M’QV/WflKX» Yxéie, KMW, 5M); Problem 3 Shown below is the desired timing of a 2-bit counter (countOut). Master Time Bar? MMMMMMMMMMMMM I ”3'33; """""""""""""" ill Pointer: Wit ffiéifi'émwm Interval; 595.59 ns Siam; End:§ i60,l0ns 24fl]0ns 320,10ns 409.0% 480.0% 860.10ns 640.10% 720.10% 806.0% 8803083 Sfifliflns lflrlus Clock Reseln - X - . ' : : 3 = , 5 I - 3 ; ' . j counlOul m— a -_-_-_———l_ =2 ‘ Zl ; : ., * E ' . ; i ' I § I 22 i Z3 % 3. Complete the ARCHITECTURE section on the m to implement the 2-bit counter with an asynchronous Resetn. ' '— lmportant notes and hints: - 0 You can determine the count sequence from the above timing diagram (countOut). o The count sequence is also affected by input X (as seen from timing diagram). . There are three more outputs (Z1, 22, and 23). They are determined by the countOut value and input X. ' o Hint: 23 is true for one clock cycle after countOut = “11”. O .1: 0 CASE statement will make your life a lot easier. ‘1/ Z ENTlTY T1Prob3 IS J/ PORT ( Clock, Resetn, X : lN STD_LOGlC ; _ 3 countOut : OUT STD_LOGlC_Vector (1 DOWNTO 0); X 0 21,22, Z3 : OUT STD_LOGlC ) ; 1 END T1 Prob3 ; : / EEL 4712 — Digital Design Test 1 -— Fall Semester 2009 Problem 3 Name ARCHITECTURE T1P3Arch OF T1Prob3 IS SIGNAL M; 5W,M$/€»Vfl/'ZW 5/ MMWF? é?) BEGIN PROCESS ( flwm) W ) BEGIN IF W: F 77/542 W4- flfl'; ' 545/457! (KM :FVFW flx/fl M: '/ ’1 may WF/E/t/ Frag); :7 ~~W= ”// ’/ ZF X= fl, fflE/V W4= ”’Vfll”) 77/51/ 234: 4 // Elf? £36.35)! 60/) /F/ ’ EM) //= 5140 @6065 ' flflaéféf( fégm" X) 56/6/4/ /F «W: ’W”)FF(W= ”// ”fl/x);(_—='/’}/) ffi/é/W %/<r='-— ‘0" £256” 5/45: (59' - {MD /F f x/P/F 5/59 V/ZOJFS/J)’ MWWFF W” 4 END T1 P3Arch; EEL 4712 — Digital Design Test 1 — Fall Semester 2009 Name Problem 4 20.“ Z1_H X zz_H 23 H Z4_L (active low) Z5_L (active low) 4. Complete the following Architecture section to implement the above circuit. . Note that Z4_L and Z5_L are active low output signals. All the other signals active high. - The signal Clock is connected to the clock inputs of all the flip-flops. . All you code must be inside the PROCESS block. ENTITY P4Circuit IS PORT( Clock, X :lN STD_ LOGIC; ZO_ H, Z1 _H ZZ_ H, ZB__ H Z4_ L, Z5_ L. OUT STD _;LOG|C) END P4Circuit; ARCHITECTURE Behavior OF P4Circuit IS MW @2333, fl/yi/xffp, Mé/c ' BEGIN -- Other than SIGNAL statements, your code must be inside the PROCESS block. PROCESS JCK BEGIN {4’4 X ) If (CféflMwQJVéWfl/KZ’ flzflCI/C’: y :2 MW £d<: X) 222%,“ Mfg? WMfl] ZLh/(r 9%? / —' JZflfl/(W 251,9!- Wa/ - fiW gfiza ' 57/} /F Zfl,A/<> a if #6.- END P%&E§S<: END Behavior m4 mym: WM g’M’Mwfi/ EEL 4712 — Digital Design Test 1 — Fall Semester 2009 Problem 5 Name BCDCounter8 Digit1[3..0] Digit0[3..0] TC 5. Complete the Architecture section (see next page) for the above BCDCounter8, which consists of two 4—bit counters (Digit1[3..0] and Digit0[3..0}). If EN = ‘1’, then BCDCount8 will - count in hex as followings: 00, 01, ...08,09,10,11, 17,18,18,18,19,20, 91,92, ..., 99,00,01,... Ki EN = ‘0' here I 0 EN is an active high “enable” input. See example above. . When Digit1,DigitO reaches hex 99, TC will become ‘1’ during that clock cycle and the BCDCounter8 resets to 00 at the next active clock transition. Be sure to follow these instructions: . PROCESS block 1: Implement the DigitO counter here. You must use a WAIT UNTIL statement. 0 PROCESS block 2: Implement the Digiti counter here. Don’t use a WAIT UNTIL statement. . You must implement TC after PROCESS block 2 and must use a conditional assignment statement. LIBRARY ieee; USE ieee.std_logic__1164.all; USE ieee.std_logic_unsigned.aII; i ENTITY BCDCounter8 IS PORT( EN, CLK : lN STD_LOG|C; Digiti, DigitO I BUFFER STD_LOG|C_VECTOR(3 downto 0); TC 2 OUT STD_LOGIC ); END BCDCounter8; -- Complete the Architecture section on the next page. I EEL 4712 -— Digital Design Test 1 — Fall Semester 2009 Pmb'em 5 Name (Problem 5 — continued) ARCHITECTURE design OF BCDCounter8 IS BEGIN -- Use this PROCESS block to implement DigitO. You must use an WAIT UNTIL statement. PROCESS BEGIN 224/417” 2/ 2 [ELK é/E/u‘“ fl/Vfl (’4 /c’ END PROCESS; --Use this PROCESS block implement Digit1. Don’t use an WAIT UNTIL statement. PROCESS (52K ) BEGIN 2f/J42’2’227/f 2242?) (“e/8*: O” 77/EW IF 5V 7’ //: [€22 J///: /&9/” 22;) 2%2’2 720/” 227’! 4 “ ’MJJ ” 5221/3 7/02 '—-7 M1 MM 7L. ZW/ 777g/z: $2727“ 7’ 1’ 5M) 05; 5712? /FJ FM 1173 END PROCESS; "Implement TC here; You must use a conditional assignment statement. 75’ <>'/ V’WFJ (27/2772 1/2727 14 1/} 22/2242 "’ 22:32?! 9 252% ’2 3 END design; 27,. ‘EEL 4712 — Digital Design Test 1 —- Fall Semester 2009 Name 6. Miscellaneous: LSA Question The signals A, B, C, and CLK represent synchronous outputs from your UF- 12 t 4712 board. The LSA is connected to your board in the following fashion: p s. - LSA channel Signal name 16 Draw the data that would be captured by the LSA, as it would appear on the screen, for each of the following scenarios: 6(a). The LSA is sampling using “Channel 31” as the clock source. Assume the first sample is taken after 30 ns. Draw your answer for part a: EEL 4712 — Digital Design Test 1 -— Fall Semester 2009 Name 6(b). The LSA is sampling using an internal 50 MHz clock source. Assume the first sample is _ taken right before 20 ns. Draw your answer for part c: - ' 6(0). For an n—bit adder, the inputs are A(n-1)..A(O) and B(n-1)..B(0) and carry-in 0(0). The outputs are SUM(n—1)..SUM(0) and carry-out C(n). (4 pts.) For an n-bit look-ahead carry generator, the equation for carry-out of stage C(i+1) = G(i) OR P(i) AND C(i) What is the equation for C(2) as a function of P(i)’s, G(i)’s, and C10) in a sum-of—product form? 6(2) = él-f P/‘ff/ :— é/ng~(é0 M’J’Kfl) = (7/ fP/é&+ fl/m'w l is: What is the equation for C(n) as a function of P(i)’s, G(i)’s and C101? You can use the notation. ‘ C(n) =®¢~l 77/624 642+ avg/é“: (I; f " fi ’ ”1’5 4/9?!" aka/fig, M @(fl EEL 4712 — Digital Design Test 1 — Fall Semester 2009 Name ENTITY _entity_name IS GENERIC(__variable_name: INTEGER := __constant_value); PORT(_input_name,_input_name :IN STD_LOGIC; _input_vector__name : IN STD_LOGIC_VECTOR(_high downto _low); _bidir__name, _bidir_name : INOUT STD_LOGIC; _output_name, ‘_outpL1t_name ' : OUT STD_LOG|C); ‘ END _entity_name; ARCHITECTURE a OF _entity_name IS SIGNAL _signal_name : STD_LOGIC; SIGNAL _signal_name : STD_LOGIC; BEGIN -- Process Statement -- Concurrent Signal Assignment -— Conditional Signal Assignment —— Selected Signal Assignment —— Component lnstantiation Statement END a; _instance_name: _component_name GENERIC MAP (_variable_name => _constant_value) PORT MAP (_component_port => _connect_port, component_port => _connect_port); WITH _expression SELECT _signal <= _expression WHEN _constant_value, _expression WHEN _constant_value, _expression WHEN _constant_value, _expression WHEN _constant_value; _signal <= _expression WHEN _boolean_expression ELSE _expression WHEN _boolean_expression ELSE _expression; IF _expression THEN <optional_label>: statement; _statement; for <loop_id> in <range> loop EL§F _expression THEN -- Sequential Statement(s) _statement; end loop; _statement; ELSE <generate_label>: statement; ‘ FOR <loop_id> IN <range> GENERATE _statement; —— Concurrent Statement(s) EN‘SIF; END GENERATE; CASE _expression IS WHEN _constant_value => _statement; _statement; WHEN _constant_value => _statement; _statement; WHEN OTHERS => _statement; _statement; END CASE; WAIT UNTIL _expression; 10 EEL 4712 — Digital Design Test 1 —— Fall Semester 2009 Name IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed wrong. - COVER SHEET: Problem: Points: 1 (16 pts) ‘1 1 Total 2 (15 pts) 3 (22 pts) ] 4 (15 pts) 5 (20 pts) ‘— 6 (12 pts) Re-Grade Information: 11 ...
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