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EEL4712T2Fall09Solution - EEL 4712 — Di ital Design Test...

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Unformatted text preview: EEL 4712 — Di ital Design Test 2 — Semester 2009 Name FALL Summag Sheet: Problem: Points: 1 (8 pts) 2 (22 pts) , 3 (17 pts) 4 (22 pts) 5 (15 pts) 6. (16 pts) Re-Grade Information: 10 EEL 4712 — Digital Design Test 2 — ' ' -. Semester 2009 Name IMPORTANT: 0 Please be neat and write (or draw) carefully throughout the test. If we cannot read it with a reasonable effort, it is assumed wrong. As always, the best answer gets the most points. 1. Miscellaneous. :hcount = O (a) VGA display calculation:vcount = 0 : here - VSYNC_END Pixel information for 4 (of 480) rows [4 x 640 pixels] VSYNC_BEGIN szellmformanon for 1 row {640 pixels) l l ( Horiz_Sync W ________________ - Vert Sync _ H YNC BEGIN ' = f 1H0riz_Sync. S — H_DISPLAY_END A 37-77 ”S l i pulsefor each : 3.77 US : HSYNC_END ; 1 Vert_Sync row refresh (480 D = 25.17 US i l E pulse for each rows per screen) screen refresh E = 0.94 US For Lab 5 assuming the board clock freguengyjfi, what constant should be use for H__ DISPLAY_ END? For credit...please show work. g i (For credit," show work here.) gé 3 (answer) (4 pts.) 5 / //.. fi/fil’éflfle‘w = ,4 ... 5' = 5 7f 77— y; W?” 5 7—; /fl 0454/; 2: /flfl75 3 é g5 ; /flfl 725 i (b) For credit show work. For Lab 6, assume the latency for the multiplier components is 6 clock cyles, the adders 10 clock cycles, and the rest of the datapath (memory, shift register, etc.) 7 clock cycles. Also assume that there are 10,000,000 words in the input stream (a new input l word is inputted every clock cycle). The board clock frequency is 25 MHz. (4 points) How many nanosec before the f_irst result is outputted? , /;Z/) nsec 774g %/0r/0= 33M7¢_ 35 X fie/x25 = /32p,¢/§ How many clock cycles before the second result lS outputted? g¢ clock cycles How manyc clock cycles sbefore a_l_l the results are outputted? fly COCCCGS ngv‘fgjf gaeflM/J 0, MI ky' ””7 f/M EEL 4712 - Digital Design Test 2 — Spl'fl'l'g Semester 2009 Name 2. ASM and VHDL. (3) Shown in Figure 1(next page) is the VHDL specification of a ASM controller. Analyze the - VHDL code and complete the following timing diagram: Specify the values for state (0, ‘l, 2, or 3), and outputs P, Q, Y, and Z. Note that there are two timing diagrams, each is independent of the other. For the last one, the initial state is given (as state = 3). Please show delays. Name: » Clock Resetn _ _--L _-44.-__4..__.—-- ._........-..-..-__‘ EEL 4712 ~ Digital Design Test 2 -— W Semester 2009 Name LIBRARY ieee ; USE ieee.std_logic_1164.ali ; ENTITY T2Prob1 IS PORT( Clock, Resetn, X, R, S : IN STD_LOGIC ; P, Q, Y. Z : OUT STD_LOGIC ) ; END T2Prob1 ; Figure 1. To be used for problem 2 ARCHITECTURE Behavior OF T2Prob1 IS SIGNAL state : STD_LOGIC_Vector (1 DOWNTO 0); BEGIN PROCESS ( Resetn, Clock) IF Resetn = '0' THEN '~'EVENT AND Clock z, '1' M” E“ WHEN "11" => state <= "01" ; WHEN "00" => IF X = '0' THEN state <= "00"; ELSE state <= "11"; END IF ; WHEN OTHERS => state <= "00"; END CASE ; END IF ; END PROCESS ; '1' WHEN state = "01" ELSE '0'; -- P is an o“ tput ’ PROCESS (state, R, S) BE \ IOI; lot; . SE state IS WHEN "01" => IF S = '0' THEN Y <= '1'; ELSE Z <= '1'; END IF; WHEN "11" => IF R = '1' THEN Y <= '1'; END IF; WHEN OTHERS => END CASE; END PROCESS; END Behavior ; EEL 4712 - Digital Design Test 2 — m Semester 2009 17 pts. 3. Cyclone ll Logic Element (LE) Given the above PROCESS block, implement it in the above Cyclone ll logic element (LE). Put your answers below. Each signal should be connected to O, 1, X (“don’t care”), NC (for not connected), (A_ (E)- PROCESS (lN1, lN2, lN3) BEGl CASE lN1 IS WHEN ‘0‘ => Z1 <= lN2 AND lN3; WHEN OTHERS => Z1 <= lN2 OR IN3; _ . ‘ SE ' lF (Clock'EVENT AND Clock = ‘1’)THEN lF lN4 = 'fl' THEN 22 <= '0'; ELSIF 1N1 = ‘1' THEN Q <= 1N3; END IF ; END IF ; END IF; END PROCESS ; (assume connec e figure 24‘ LE :1: Namath/99:19 IN1 D— IN2 D— , - - - Regsterchain |N3 D'— cmnectien lN4 D— 3 CLOCK D— g R C l ' |N1 damn i 0:2!th @3330:an Z1 |N2 data-2 lN3 detail tin (from Gout of previous LEE) Flow. Cale1n,. and Direct Link Framing (Quack (mew .1 ' _~_ (F) aha fl-AB Wilda: (G) flair MBWME] date-1'4 I Register Feedeaok or a signal name. if it is “don’t care”, you must put X (not 0 or 1). 3 x l l l E l l l EEL 4712 — Digital Design Test 2 — Sling Semester 2009 Name 4. AltSynRam Problem . . am; Depth = 256; Width = 8; Address_radix = hex; Data__radix = hex; Content Begin 00 : 80; 07 : 87; 01:81; .08 : 88; 02 : 82; 09 : 89; ; 03 : 83; 0A: 8A; 04 : 84; DB : 8B; : 85; OC : 8C; Complete the following timing diagram. 'Assume all flip—flops are initialized to ‘0’. Both RAM’s has the same data (ramdatmif). ................................................................... . aDATAln aWRaddr aWRen bDATAln ; _ bWRaddr bWRen _ _ ._ _ _ _. - _ _ - - _ _ _ - - _ _. ________________________________________________ EEL 4712 — Digital Design. Test 2 —- 81mins Semester 2009 Name 15 pts. 5. Using altsyncram to implement a FIFO (First-in-first-out) component FIFO rdreq: - O: The output q[31..0] will hold the last value outputted from the FIFO. 0 1: The next value in the FIFO will be outputed from the FIFO q[31..0] at the next active clock transition. ' wrreq: o O: The output q[31..0] will hold the last value outputted from the FIFO. 0 1: data[31:0] will be written in next location in the FIFO at the next active ! clock transition. (Output q[31:0] will hold last value outputted.) - ‘ empty: 32 m X 256 words . O: The FIFO is not empty (Some inputted values have not been outputted). sclr: syncrhonous clear 1: The FIFO is empty. If a “rdreq” is asserted, then “junk” data will be to “empty” the FIFO outputted. (a) Give me the VHDL statement(s) )to produce the "’empty output (3 pts.) 7#/E,¢/ WK g £45! Wfig Effie?) ”if???“ if block diaoram -» datal3l ..01 {$31-01 * wrreq ....... . rdreq empty twig?" (b) Complete the design of the FIFO by making the required connections below (For clarity, use labels when appropriate). Add any logic if necessary. (12 pts.) FIFO (design) data[31..0 l i l l i l l l wrreq— rdreq — 8-bit counter ’ en q[7:0] clr fifoclk —— sclr —_— _ . 8-bit counter EEL 4712 — Digital Design Test 2 — “Semester 2009 Name 6. FIR filter Datapath component, using GENERATE statement Shown on the next page is the example code that we discussed in class for a 4-stop FIR filter. (a) Give me the code required to implement the required 4-bit shift registers to produce reg(4 DOWNTO 1). (6 pts.) 0 Restriction: ou have to GENERATE and PORT MAP statements for this art 0 Assume that you have the following component: @{j fig ,2, fly? [ COMPONENT dff IS j[)/Z;? ) Mg a?) PORT( clock: lN STD_ LOGICW g/y d: IN STD_ LOGIR q. OUT STD_ L‘OGlC ); VWW? 3 END COMPONENT; \ngégfigjlfilv :) . Important note: reg(O) is the input to the reg(1) flip—flops which contain the most! recent data- reg(O) should be connected to the datapath input signal named‘ in.Data” (Put your answer here, including any new TYPE or SIGNAL definitions) W, Fag ’4‘ 17V / 729 a" cféflfléflfz Wflk % we Mflf/WMM> 49% 42> flay/z (J ; =7/ng) 191/} éé’flé’xfiff m «(was mflfliét‘ MW?” 2 f (b) Give me the code required to implement all the adders of the R filter datapath component, producing the datapath output signal named “ (8 pts.) 0 Restriction: When ossible ou have to GENERATE and PORT MAP statements. (Put your answer here, including any new TYPE or SIGNAL definitions) aflg: wt? ,{r J‘x/z m 2 Way Mg” : M ”(9/37 Wflflfgfigg “7/ We w>wxeeaffg a” “U Mb 5) WW{24<A)) W ~> Maggy-{1 )) W t) Maw/Id EEL 4712 — Digital Design Test 2 —- Spfifig Semester 2009 Name (0) Given the following decimal number -10.687{(which is -1010.1011 in binary), convert it to the lEEE 754 loating~point format: (2 pts.) __/%)0/0/0/ ff X ,2 . Bit 31: sign bit =~ o Bits 30-23: exponent (with a bias of 127 = 111 ,1; 11 in blnary) WI... 0 Bits 22-0: mantissa ‘\/0&le. :9 S Bits 30—23 Ex nent . Bits 22—0 Mantissa % / MELZL / fl M d/Ld d—éLagToE/Igld oalaalbla and GENERATE statement 3 ‘v ‘45....4Ww»: —— snippet of code to demonstrate Multi-dimensiona arr ARCHITECTURE struct OF datapath IS -- Definition of other components COMPONENT multiplier ls PORT ( clock: lN STD_LOGIC; dataa : lN STD_LOGlC_VECTOR(31 DOWNTO 0); datab : lN STD_LOGlC_VECTOR(31 DOWNTO 0); result: OUT STD_LOGlC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT adder IS PORT ( clock : IN STD_LOGIC ; dataa : IN STD_LOGlC_VECTOR (31 DOWNTO O); datab : IN STD_LOGlC_VECTOR (31 DOWNTO 0); result : OUT STD_LOGlC_VECTOR (31 DOWNTO 0) ); END COMPONENT; SUBTYPE signalVectors IS STD_LOGlC_VECTOR(31 DOWNTO 0); TYPE array40fSignaIs IS ARRAY(4 DOWNTO 1) OF signalVectors; TYPE array50fSignals IS ARRAY(4 DOWNTO 0) OF signalVectors; SIGNAL coeff: array40fSignals; SIGNAL reg: array50fSignals; —- reg(4 DOWNTO 1) are outputs of the 4 registers -- reg(O) is the input to the flip-flops with the most recent data SIGNAL mout: array40fSignals; ; BEGIN —- Assume that coeff(4 DOWNTO 1) have been assigned here for your use. -- shift register code mults: FOR i IN 1 to 4 GENERATE multArray : multiplier PORT MAP (clock=>clk, dataa=>coeff(i), datab=>reg(i), result=>mout(i)); END GENERATE mults; ’ -- code for adders END struct; ' ...
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