EEL4712T2Sp09

# EEL4712T2Sp09 - EEL 4712 Digital Design Test 2 Spring...

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EEL 4712 – Digital Design Test 2 – Spring Semester 2009 Name ___________________________________ 1 IMPORTANT: Please be neat and write (or draw) carefully throughout the test. If we cannot read it with a reasonable effort, it is assumed wrong. As always, the best answer gets the most points. 1. Miscellaneous. (a) Clock debouncing using a shift register and a clock divider Design a switch debouncing circuit using a clock divider and a shift register (with an AND gate) with the following assumptions: The bouncing period of a switch is determined to be 8 milli-seconds. The system clock is 20 MHz The clock divider is designed using 16 flip-flops. What is the minimum number of flip-flops can be used for the shift register that will “cover” the bounding period of the switch? (For credit, show work here.) _________________ (answer) (5 pts.) (b) VGA display calculation: 10 pts. Video_On Horiz_Sync Vert_Sync Pixel information for 1 row (640 pixels) Pixel information for 4 (of 480) rows [4 x 640 pixels] 1 Vert_Sync pulse for each screen refresh 1 Horiz_Sync pulse for each row refresh (480 rows per screen) HSYNC_BEGIN HSYNC_END VSYNC_BEGIN VSYNC_END H_DISPLAY_END etc. Pixel information for 4 (of 480) rows [4 x 640 pixels] VSYNC END hcount = 0 vcount = 0 here D B E A A = 37.77 uS B = 3.77 uS D = 25.17 uS E = 0.94 uS For Lab 5, assuming the board clock frequency is 20 MHz, what constant should be use for HSYNC_END? For credit, please show work. (For credit, show work here.) _________________ (answer) (5 pts.)

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EEL 4712 – Digital Design Test 2 – Spring Semester 2009 Name ___________________________________ 2 2. ASM/VHDL. Given below is a timing diagram (functional simulation) showing the desired timings among the states and signals of a controller. (a) Construct an ASM diagram that will produce the above behavior. (8 pts.) (b) Complete the VHDL specification (on the next page) of your ASM diagram. Please don’t change the structure of the code. In other words, you have to use the second CASE statement to implement the conditional and unconditional outputs. (10 pts.) ENTITY Test2P2 IS PORT ( Clock, Resetn, InX : IN STD_LOGIC ; -- Resetn is active low, asynchronous OutY, OutZ : OUT STD_LOGIC ) ; END Test2P2 ; 18 pts. S2 S2 S2 S2 S1 S1 S0
Test 2 – Spring Semester 2009 Name ___________________________________ 3 2(b) ARCHITECTURE ASMArch OF Test2P2 IS TYPE ASMstateType IS (S0, S1, S2) ; -- User defined signal type SIGNAL state : ASMstateType ; BEGIN PROCESS ( ) -- state transitions BEGIN IF Resetn = '0' THEN ELSIF ( ) THEN CASE state IS WHEN S0 => WHEN S1 => WHEN S2 => END CASE ; END IF ; END PROCESS ; PROCESS ( ) -- conditional and uncond. outputs BEGIN CASE state IS – You have to use this CASE statement for the outputs. WHEN S0 =>

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EEL4712T2Sp09 - EEL 4712 Digital Design Test 2 Spring...

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