esweek10_if - IntermediateFabrics:VirtualFPGA James Coole...

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Click to edit Master subtitle style Intermediate Fabrics: Virtual FPGA  Architectures for Circuit Portability and Fast  Placement and Routing on FPGAs James Coole PhD student, University of Florida Dr. Greg Stitt Assistant Professor of ECE, University of Florida CODES+ISSS ‘10
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Introduction 22 Problem: Lengthy, increasing FPGA place & route (PAR) times are a design bottleneck PAR Time Previous work: Fabrics specialized for fast PAR [Lysecky04] [Beck05] [Vahid08]
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Introduction 33 Ideally we want the advantages of fast PAR with the flexibility and availability of COTS FPGAs Approach: virtualize specialized architecture on COTS FPGA
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Approach 44 n Definition q Intermediate fabric (IF): a PAR-specialized reconfigurable architecture implemented on top of COTS FPGAs q Serves as a virtualization layer between netlist/circuit and FPGA n Motivations q Orders of magnitude PAR speedups are possible for coarse-grain architectures n Reduction in problem size compared to FPGA PAR (e.g. multipliers not mapped to LUTs) q Portability of IF configuration between any FPGAs implementing the same IF n Enables portable 3rd party PAR tools q Enables small embedded PAR tools for run- time construction of datapaths n e.g. dynamic binary translation [Stitt07] [Beck05] on COTS devices n Challenge: virtualization overhead Fast PAR Portability
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Previous Work 55 n Dynamic FPGA routing and JIT compilation [Lysecky04][05] q 3x PAR speedup q Requires specialized device architecture n Coarse grain reconfigurable device architectures [Becker01] [Ebeling96] […] q Faster PAR because of reduced problem size compared to FPGAs q Domain specific, not as flexible as fine-grain FPGAs n Wires on Demand [Athanas07] q Fast PAR by routing between pre-PARed modules q Could be complementary, with IFs being used for PAR of modules n Quku [Shukla06] q Coarse-grained array of ALUs implemented on FPGA q Essentially one instance of an IF q IFs also address PAR execution time and portability
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IF Architecture 66 n Implemented in multiple planes – groups of resources with similar responsibilities and a purpose-specialized interconnect q Stream plane : includes interfaces to off-chip memories and support for buffering q Control plane: resources for implementing control, such as state machines q Data plane: resources for computation and data steering * n Overhead: logic utilization and device area required to support fabric configuration q Slice/LUT overhead primarily due to interconnect of data plane q Flip-flops due to configuration bits and interconnect pipelining * primary source of overhead
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