rc_architecture_1.8

rc_architecture_1.8 - Reconfigurable Architectures Greg...

Info iconThis preview shows pages 1–11. Sign up to view the full content.

View Full Document Right Arrow Icon
Reconfigurable Architectures Greg Stitt ECE Department University of Florida
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
How can hardware be reconfigurable? Problem: Can’t change fabricated chip ASICs are fixed Solution: Create components that can be made to function in different ways
Background image of page 2
History SPLD – Simple Programmable Logic Device Example: PAL (programmable array logic) PLA (programmable logic array Basically, 2-level grid of “and” and “or” gates Program connections between gates Initially, used fuses/PROM Could only be programmed once! GAL (generic array logic) allowed to be reprogrammed using EPROM/EEPROM But, took long time Implements hundreds of gates, at most [Wikipedia]
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
History CPLD – Complex Programmable Logic Devices Initially, was a group of SPLDs on a single chip More recent CPLDs combine macrocells/logic blocks Macrocells can implement array logic, or other common combinational and sequential logic functions [Xilinx]
Background image of page 4
Current/Future Directions FPGA (Field-programmable gate arrays) - mid 1980s Misleading name - there is no array of gates Array of fine-grained configurable components Will discuss architecture shortly Currently support millions of gates Coarse-grained RC architectures Array of coarse-grained components Multipliers, DSP units, etc. Potentially, larger capacity than FPGA But, applications may not map well Wasted resources Inefficient execution
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
FPGA Architectures How can we implement any circuit in an FPGA? First, focus on combinational logic Example: Half adder Combinational logic represented by truth table What kind of hardware can implement a truth table? Input Out A B S 0 0 0 0 1 1 1 0 1 1 1 0 Input Out A B C 0 0 0 0 1 0 1 0 0 1 1 1
Background image of page 6
Look-up-tables (LUTs) Implement truth table in small memories (LUTs) Usually SRAM A B S 0 0 0 0 1 1 1 0 1 1 1 0 A B C 0 0 0 0 1 0 1 0 0 1 1 1 0 1 1 0 Addr Output 0 0 0 1 Output Logic inputs connect to address inputs, logic output is memory output 2-input, 1-output LUTs 00 01 10 11 00 01 10 11 A B Addr A B S C
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Look-up-tables (LUTs) Alternatively, could have used a 2-input, 2-output LUT Outputs commonly use same inputs 0 1 1 0 S 0 0 0 1 C 0 1 1 0 S 0 0 0 1 C 00 01 10 11 00 01 10 11 00 01 10 11 Addr A B Addr A B Addr A B
Background image of page 8
Look-up-tables (LUTs) Slightly bigger example: Full adder Combinational logic can be implemented in a LUT with same number of inputs and outputs 3-input, 2-ouput LUT Inputs Outputs A B Cin S Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1 A B Cin S Cout Truth Table 3-input, 2-output LUT
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Look-up-tables (LUTs) Why aren’t FPGAs just a big LUT? Size of truth table grows exponentially based on # of inputs 3 inputs = 8 rows, 4 inputs = 16 rows, 5 inputs = 32 rows, etc. Same number of rows in truth table and LUT
Background image of page 10
Image of page 11
This is the end of the preview. Sign up to access the rest of the document.

This document was uploaded on 07/12/2011.

Page1 / 65

rc_architecture_1.8 - Reconfigurable Architectures Greg...

This preview shows document pages 1 - 11. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online