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Unformatted text preview: Reconfigurable Architectures Greg Stitt ECE Department University of Florida How can hardware be reconfigurable? Problem: Cant change fabricated chip ASICs are fixed Solution: Create components that can be made to function in different ways History SPLD Simple Programmable Logic Device Example: PAL (programmable array logic) PLA (programmable logic array Basically, 2level grid of and and or gates Program connections between gates Initially, used fuses/PROM Could only be programmed once! GAL (generic array logic) allowed to be reprogrammed using EPROM/EEPROM But, took long time Implements hundreds of gates, at most [Wikipedia] History CPLD Complex Programmable Logic Devices Initially, was a group of SPLDs on a single chip More recent CPLDs combine macrocells/logic blocks Macrocells can implement array logic, or other common combinational and sequential logic functions [Xilinx] Current/Future Directions FPGA (Fieldprogrammable gate arrays)  mid 1980s Misleading name  there is no array of gates Array of finegrained configurable components Will discuss architecture shortly Currently support millions of gates Coarsegrained RC architectures Array of coarsegrained components Multipliers, DSP units, etc. Potentially, larger capacity than FPGA But, applications may not map well Wasted resources Inefficient execution FPGA Architectures How can we implement any circuit in an FPGA? First, focus on combinational logic Example: Half adder Combinational logic represented by truth table What kind of hardware can implement a truth table? Input Out A B S 1 1 1 1 1 1 Input Out A B C 1 1 1 1 1 Lookuptables (LUTs) Implement truth table in small memories (LUTs) Usually SRAM A B S 1 1 1 1 1 1 A B C 1 1 1 1 1 1 1 Addr Output 1 Output Logic inputs connect to address inputs, logic output is memory output 2input, 1output LUTs 00 01 10 11 00 01 10 11 A B Addr A B S C Lookuptables (LUTs) Alternatively, could have used a 2input, 2output LUT Outputs commonly use same inputs 1 1 S 1 C 1 1 S 1 C 00 01 10 11 00 01 10 11 00 01 10 11 Addr A B Addr A B Addr A B Lookuptables (LUTs) Slightly bigger example: Full adder Combinational logic can be implemented in a LUT with same number of inputs and outputs 3input, 2ouput LUT Inputs Outputs A B Cin S Cout 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A B Cin S Cout Truth Table 3input, 2output LUT Lookuptables (LUTs) Why arent FPGAs just a big LUT? Size of truth table grows exponentially based on # of inputs 3 inputs = 8 rows, 4 inputs = 16 rows, 5 inputs = 32 rows, etc....
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This document was uploaded on 07/12/2011.
 Spring '09

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