Lecture 7

Lecture 7 - ECE52 Spring 10 Lecture 7 1/28/11 Homeworks 4,...

Info iconThis preview shows pages 1–8. Sign up to view the full content.

View Full Document Right Arrow Icon
1 ECE52 Spring 10 Lecture 7 1/28/11 Homeworks 4, 5 posted Labs 2, 2b posted
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 Negative Logic (shudder) We mentioned briefly the choice of high voltage for 1 and low voltage for 0 was arbitrary (but sensible!) Negative logic makes the opposite choice – but the transistors still work as they always do! NMOS conducts when input high, PMOS conducts when input low
Background image of page 2
3 (a) Positive logic truth table and gate symbol f 0 0 1 1 0 1 0 1 1 1 1 0 x 1 x 2 f x 1 x 2 (b) Negative logic truth table and gate symbol 1 1 0 0 1 0 1 0 0 0 0 1 x 1 x 2 f f x 1 x 2
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4 PLD’s SSI components like our 7400 series gates are useful but tiny, and of fixed function; it takes a lot of them to build a complex function Custom VLSI can design a chip (just a network of transistors, after all!) to implement any function but cost is extreme for the first one
Background image of page 4
5 Programmable Logic Devices Generic “seas of gates” with programmable interconnections sometimes one-time programmable, sometimes reprogrammable either statically or even dynamically! Most PLDs are organized like our SOP networks – “AND” plane followed by “OR” plane PLD is the generic term, PAL, PLA, CPLD, FPGA are all specific types of PLD; the first 3 are similar, FPGAs are radically different!
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
6 General PLA structure f 1 AND plane OR plane Input buffers inverters and P 1 P k f m x 1 x 2 x n x 1 x 1 x n x n PLA: Programmable Logic Array
Background image of page 6
7 Figure 3.26. Gate-level diagram of a PLA. f
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 8
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 28

Lecture 7 - ECE52 Spring 10 Lecture 7 1/28/11 Homeworks 4,...

This preview shows document pages 1 - 8. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online