Lecture 11_001

Lecture 11_001 - ECE52 Spring 11 Lecture 11 2/7/11 75...

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1 ECE52 Spring 11 Lecture 11 2/7/11 75 minute class Wednesday 2/9/11 1:15-2:30 No class Friday 2/11/11
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2 Lab Reports Abstract - 10 points Objective Result summary Conclusion Simulation/Pre-Lab - 30 points Derivation of design equations Simulation results/waveforms Block diagrams/VHDL of pre-lab designs Results - 25 points Brief description of in-lab observations Measurement tabulations Analysis - 35 points
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3 VHDL, take 2 We introduced VHDL with just BIT types – legal values 0 and 1 only, but we have seen that Z and d (high impedance and don’t care) are also important states in practical circuits; will be Z and “–” in VHDL. Thus type “STD_LOGIC” instead of type “BIT” for practical work. A defined type, must explicitly include libraries to invoke it.
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4 LIBRARY ieee ; USE ieee.std logic_1164.all ; ENTITY func1 IS PORT ( x1, x2, x3 : IN STD_LOGIC ; f : OUT STD_ LOGIC ) ; END func1 ; ARCHITECTURE LogicFunc OF func1 IS BEGIN f <= (NOT x1 AND NOT x2 AND NOT x3) OR (NOT x1 AND x2 AND NOT x3) OR (x1 AND NOT x2 AND NOT x3) OR (x1 AND NOT x2 AND x3) OR (x1 AND x2 AND NOT x3) ; END LogicFunc ; The very first example in chapter 4. Minimized to f=x3’+x1x2’ VHDL for this example – input in canonical SOP form. The function f (x1, x2, x3) = Σ m (0, 2, 4, 5, 6).
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5 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY adder4 IS PORT ( Cin : IN STD LOGIC ; x3, x2, x1, x0 : IN STD_LOGIC ; y3, y2, y1, y0 : IN STD_LOGIC ; s3, s2, s1, s0 : OUT STD_LOGIC ; Cout : OUT STD_LOGIC ) ; END adder4 ; ARCHITECTURE Structure OF adder4 IS SIGNAL c1, c2, c3 : STD_LOGIC ; COMPONENT fulladd PORT ( Cin, x, y : IN STD_LOGIC ; s, Cout : OUT STD_LOGIC ) ; END COMPONENT ; BEGIN stage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ; stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ; stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ; stage3: fulladd PORT MAP ( Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ; END Structure ; LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fulladd IS PORT ( Cin, x, y : IN STD_LOGIC; s,Cout : OUT STD_LOGIC; END fulladd; ARCHITECTURE LogicFunc OF fulladd IS BEGIN s <= x XOR y XOR Cin ; Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ; END LogicFunc ;
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6 Structural VHDL
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Lecture 11_001 - ECE52 Spring 11 Lecture 11 2/7/11 75...

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