Lecture 12

# Lecture 12 - ECE52 Spring 11 Lecture 12 2/9/11 75 minute...

This preview shows pages 1–13. Sign up to view the full content.

1 ECE52 Spring 11 Lecture 12 2/9/11 75 minute class No class 2/11/11 Midterm 2/18/11

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
2 Espresso – your logic minimization friend Your book eventually gets around to mentioning espresso briefly near the end of chapter 4 espresso is an algorithm from UC Berkeley to find a pretty good minimal form (not necessarily the absolute minimum) of a logic function related to Quine-McCluskey algorithm we will discuss later from the early days of PLD’s
3 Espresso example – adder [login-vm.ee.duke.edu]110: cat adder.esp # full carry adder .i 3 .o 2 000 00 001 01 010 01 011 10 100 01 101 10 110 10 111 11 [login-vm.ee.duke.edu]111: espresso < adder.esp # full carry adder .i 3 .o 2 .p 7 100 01 010 01 001 01 111 01 -11 10 1-1 10 11- 10 .e

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
4 Espresso documentation http://www.ee.duke.edu/~jab/ece52/espress o.5.html - the file format – most useful http://www.ee.duke.edu/~jab/ece52/espress o.1.html - the command options – less useful
Logic Friday Free Windows graphical tool using espresso in the back end for logic minimization and manipulation Truth tables Schematic capture Equations SOP/POS outputs Available at http://sontrak.com/ 5

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
6 Dual Rail Logic An example of when “minimizing cost and/or size” is no longer the desired metric Interesting seminar at Duke a few years back: Smart Cards – differential power attacks link to another talk on how the attacks w Dual Rail Logic is one response to such attacks
7 Problem: processing some bit patterns uses more power than others Allows attacker to infer information about cryptographic keys One solution: design logic networks that use the same amount of power for all input patterns – exploits duality we have already discussed! Dual Rail approach: always process an input and its complement, always generate result and its complement

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
8 OR-gate example From http://www.cs.berkeley.edu/~daw/papers/dualrail-tr.pdf
Back to factoring Supporting mux and pseudo-mux implementations of functions as found in FPGAs 9

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
10 Monday 2/7: Problem 3.46 Can be implemented with perfectly normal FPGA muxes with downloaded truth tables slight notation change in way they are drawn
11 A case where advantage is more apparent – I don’t expect you to reproduce this! x 1 x 2 x 3 x 4 00 01 11 10 00 01 11 10 x 1 x 2 x 3 x 4 00 01 11 10 1 1 1 1 1 1 1 00 01 11 10 1 x 5 0 = x 5 1 = (a) Karnaugh map for the function f 1 1 1 1 1 1 1 1 x 1 x 2 x 5 x 4 f x 3 g k (b) Circuit obtained using decomposition Example 4.7 in your book - Manipulations are not at all obvious (at least to me!) but result is a circuit with total cost 30 instead of 55 in conventional minimal SOP/POS form Book punts – says CAD tools have to try “an enormous number” of possible decompositions – beyond the scope of this book!

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Factoring techniques reduce LUT consumption For 7-variable example earlier in chapter (a) Sum-of-products realization x 6 x 4 f x 5 0 x 7 x 2 x 3 x 2 x 7 x 4 x 5 0 x 6 x 1 x 3 x 1
This is the end of the preview. Sign up to access the rest of the document.

## This note was uploaded on 07/05/2011 for the course ECE 52 taught by Professor Dr.jonathanboard during the Spring '11 term at Duke.

### Page1 / 39

Lecture 12 - ECE52 Spring 11 Lecture 12 2/9/11 75 minute...

This preview shows document pages 1 - 13. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online