Lecture 20

Lecture 20 - ECE52 Spring 11 Lecture 20 2/28/11 1 Memory...

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1 ECE52 Spring 11 Lecture 20 2/28/11
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2 Memory element zoo cells SRAM/DRAM plus flop - Flip Latch T D K - J R - S gated - non sensitive level sensitive edge
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3 Gated SR latch again assuming no propagation delay… first use of “clk” as our enable – suggesting how we will use it! We will call this “ level-sensitive Note here S’ is S-prime, not S-bar!!!
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4 Gated SR latch with NAND gates identical behavior to previous; fewer transistors in CMOS S R Clk Q Q
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5 Explicit Set-Reset makes sense sometimes… but D latches often more useful D: “Data” latch – remembers last value seen on D input while clock was high. Again, level-sensitive clocking. Here the two outputs are strictly complementary! Much more convenient for holding binary numbers, for instance!
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6 Timing delays t su t h Clk D Q Your book gets around to realistic timing in section 7.3.1.
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Lecture 20 - ECE52 Spring 11 Lecture 20 2/28/11 1 Memory...

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