Lecture 25

Lecture 25 - ECE52 Spring 11 Lecture 25 3/18/11 1 Basic...

Info iconThis preview shows pages 1–16. Sign up to view the full content.

View Full Document Right Arrow Icon
1 ECE52 Spring 11 Lecture 25 3/18/11
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 Basic register (!) Left out of your books! “Parallel-in, Parallel-out.” Nothing more than a bunch of flip flops we regard as a unit. You don’t need to be a shift register to be a register! (though in practice most probably will be.) I have added 2 enable signals to control the FFs. D Q Q Clock D Q Q D Q Q D Q Q In1 Q 1 Q 2 Q 3 Q 4 Input_enable Out1 Out2 Out3 Out4 Output_enable In2 In3 In4
Background image of page 2
3 Register File Reg0 n Reg1 CLK IE 1 OE 1 n Reg2 n
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4 Register File Reg0 n Reg1 CLK IE 1 OE 1 n Reg2 n
Background image of page 4
5 Register File Reg0 CLK IE 0 OE 0 n Reg1 CLK IE 1 OE 1 n Reg2 CLK IE 2 OE 2 n Adder/ALU ALU_OUT_ENA n
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
6 Register File Reg0 CLK IE 0 OE 0 n Reg1 CLK IE 1 OE 1 n Reg2 n Adder/ALU ALU_OUT_ENA n
Background image of page 6
7 Simple Shift Register Shifting numbers left or right by 1 bit will be common operations in digital computers (recall: left-shift == multiply by 2; right-shift==divide by 2) This circuit simply delays the input by 4 clock cycles Can you use latches here instead of flip-flops? D Q Q Clock D Q Q D Q Q D Q Q In Out t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 1 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 Q 1 Q 2 Q 3 Q 4 Out = In (b) A sample sequence (a) Circuit Q 1 Q 2 Q 3 Q 4
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
8 More useful: parallel/serial in/out shift register Q 3 Q 2 Q 1 Q 0 Clock Parallel input Parallel output Shift/Load Serial input D Q Q D Q Q D Q Q D Q Q would be more useful still if there was option to simply hold the data! Here, we either overwrite all 4 bits or shift them each clock
Background image of page 8
9
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
10
Background image of page 10
11
Background image of page 11

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
12
Background image of page 12
13
Background image of page 13

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
14 Muxes for logic LUT approach taken in FPGAs – code truth table – XOR example – straightforward but potentially inefficient! (a) Implementation using a 4-to-1 multiplexer f w 1 0 1 0 1 w 2 1 0 0 0 1 1 1 0 1 f w 1 0 w 2 1 0
Background image of page 14
More efficient design ( for general mux, not LUT) 0 1 0 0 1 1 1 0 1 f w 1 0 w 2 1 0 0 1 f w 1 w 2 w 2 Modified truth table f w 2 w 1 Circuit one 2-input mux instead of one 4-input mux! just a lucky coincidence or a general design principle here? nb NOT directly suited for FPGA LUT implementation where inputs are constant!
Background image of page 15

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 16
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 35

Lecture 25 - ECE52 Spring 11 Lecture 25 3/18/11 1 Basic...

This preview shows document pages 1 - 16. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online