Lecture 26

# Lecture 26 - ECE52 Spring 11 Lecture 26 3/21/11 1 Priority...

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1 ECE52 Spring 11 Lecture 26 3/21/11

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2 Priority encoders Often, one-hot input encoding is not feasible – i.e. encode which of 8 alarm stations has been activated – what if more than one has been pulled?
3 Input 0 0 Input 1 0 Input 2 0 Input 3 0 Input 4 0 Input 5 0 Input 6 1 Input 7 0 Output 1 1 8:3 Priority Encoder Output 2 1 Output 0 0 2 n inputs n outputs 110 indicates line 6 is highest priority line (only one here) currently active. z indicates at least one line active. Priority encoders higher priority Output z 1

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4 Input 0 0 Input 1 0 Input 2 1 Input 3 0 Input 4 0 Input 5 0 Input 6 1 Input 7 0 Output 1 1 8:3 Priority Encoder Output 2 0 Output 0 0 2 n inputs n outputs 010 indicates line 2 is highest priority line currently active; z indicates at least one line is active. Priority encoders higher priority Output z 1
5 Truth table – priority encoder Note – opposite of priority order in book’s example! here w0 is high priority w7 is low w7 w6 w5 w4 w3 w2 w1 w0 y2 y1 y0 z 0 0 0 0 0 0 0 0 d d d 0 x x x x x x x 1 0 0 0 1 x x x x x x 1 0 0 0 1 1 x x x x x 1 0 0 0 1 0 1 x x x x 1 0 0 0 0 1 1 1 x x x 1 0 0 0 0 1 0 0 1 x x 1 0 0 0 0 0 1 0 1 1 x 1 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 1 1 1 1 distinction between d and x? 2-level SOP certainly possible, but insight in book for more elegant design

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6 The PLDs on our boards… In labs 2 and 3 you used two different PLDs for the first time – our boards are really two completely separate systems packaged on the same board Altera MAX – CPLD technology Altera FLEX – FPGA technology Neither is state-of-the-art; boards are 10 years old, but similar except in scale to more modern versions!
7 Altera MAX 7000 CPLDs EEPROM-based CPLD, not an FPGA! 32-512 macrocells (ours 128); each with programmable AND-fixed OR plane

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8 Macrocell layout 5 product terms per macrocell plus expansion terms from other macrocells for larger functions
9 Table 1. MAX 7000B Device Overview (2.5 V) Feature Device EPM7032B EPM7064B EPM7128B EPM7256B EPM7512B Usable Gates 600 1,250 2,500 5,000 10,000 Macrocells 32 64 128 256 512 Maximum User I/O Pins 36 68 100 164 212 t PD (ns) (1) 3.5 3.5 4.0 5.0 5.5 t SU (ns) (2) 2.1 2.1 2.5 3.3 3.6 t FSU (ns) (3) 1.0 1.0 1.0 1.0 1.0 t CO1 (ns) (4) 2.4 2.4 2.8 3.3 3.7 f CNT (MHz) (5) 303.0 303.0 243.9 188.7 163.9 Package I/O Pins 44-Pin PLCC (6) 36 44-Pin TQFP (7) 36 36 49-Pin Ultra FineLine BGA ® (8) 36 41 100-Pin TQFP 68 84 84 100-Pin FineLine BGA (9) 68 84 144-Pin TQFP 100 120 120 169-Pin Ultra FineLine BGA 141 141 208-Pin PQFP (10) 164 176 256-Pin FineLine BGA 100 164 212 256-Pin BGA (11) 212 Similar to the chip on our boards but not identical – ours is too old!

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Altera FLEX 10K FPGAs CPLD (like MAX) is persistent – once programmed, it will retain its configuration until reprogrammed FPGA needs to be reprogrammed each time power is applied!
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## This note was uploaded on 07/05/2011 for the course ECE 52 taught by Professor Dr.jonathanboard during the Spring '11 term at Duke.

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Lecture 26 - ECE52 Spring 11 Lecture 26 3/21/11 1 Priority...

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