Lecture 27

Lecture 27 - ECE52 Spring 11 Lecture 27 3/23/11 Midterm 2:...

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1 ECE52 Spring 11 Lecture 27 3/23/11 Midterm 2: Friday 4/8/11 Lunch this Friday: Programming education?
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2 Almost like OO Programming in VHDL… PROCESS statement variables are the “sensitivity list” for the process here, all input variables for the mux If the value of any “sensitive” variable changes, the process is invoked here, just a single IF_THEN_ELSE but could be many statements all statements in the process evaluated in sequential order – now it really is like a program! “Any assignments made to signals inside the process are not visible outside the process until all of the statements in the process have been evaluated.” so that if there are multiple assignments to a given signal only the last one becomes visible to the rest of the system
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3 Example of overridden signals LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE Behavior OF mux2to1 IS BEGIN PROCESS ( w0, w1, s ) BEGIN f <= w0 ; IF s = '1' THEN f <= w1 ; END IF ; END PROCESS ; END Behavior ; f<= w0 sets up the default value of f; final assign overrides if s=1. Order definitely matters now! IF we switch…
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4 Incorrect ordering when order matters LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE Behavior OF mux2to1 IS BEGIN PROCESS ( w0, w1, s ) BEGIN IF s = '1' THEN f <= w1 ; END IF ; f <= w0 ; END PROCESS ; END Behavior ; Flipping the order of the statements (harmless in concurrent assignment) here changes everything
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5 Implied memory: 1-bit comparator Correct code LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY compare1 IS PORT ( A, B : IN STD_LOGIC ; AeqB : OUT STD_LOGIC ) ; END compare1 ; ARCHITECTURE Behavior OF compare1 IS BEGIN PROCESS ( A, B ) BEGIN AeqB <= '0' ; IF A = B THEN AeqB <= '1' ; END IF ; END PROCESS ; END Behavior ; As before, default case and conditional override
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6 If you leave out the default case… LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY implied IS PORT ( A, B : IN STD_LOGIC ; AeqB : OUT STD_LOGIC ) ; END implied ; ARCHITECTURE Behavior OF implied IS BEGIN PROCESS ( A, B ) BEGIN IF A = B THEN AeqB <= '1' ; END IF ; END PROCESS ; END Behavior ; VHDL says if code does not specify value of signal, retain the current value – so once A=B, nothing will change AeqB – there is implied memory for “AeqB=1”
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Resulting circuit XOR detects equality, OR insures it never changes back. .! Here this is a bad thing – an incorrect comparator circuit But this implied memory will be useful when we start modeling memory elements where this is what we want to happen! A
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Lecture 27 - ECE52 Spring 11 Lecture 27 3/23/11 Midterm 2:...

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