Lecture 28

Lecture 28 - ECE52 Spring 11 Lecture 28 3/25/11 Midterm 2...

Info iconThis preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
1 ECE52 Spring 11 Lecture 28 3/25/11 Midterm 2 4/8/11
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 Counters – could specify structurally in terms of flip flops, but… Again, we can just specify behavior! 4-bit up-counter w/enable and reset: nb count is internal (signal) Optional – for clarity since OUT values can’t be used in an expression
Background image of page 2
3 Or, since counters count integers… 4-bit up counter with parallel load Again, more examples in chapter 7 Uses BUFFER mode ports! Obviates internal signal for FFs – can use BUFFER values in expressions
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4 VHDL for general FSM Could always just do structural VHDL for resulting circuit, but rather defeats the point! VHDL supports the notion of states – we can define our own data types – assuming we have developed the state diagram for a FSM, we can code it directly!
Background image of page 4
5 Moore-type FSM 1 LIBRARY ieee ; 2 USE ieee.std_logic_1164.all ; 3 ENTITY simple IS 4 PORT ( Clock, Resetn, w : IN STD_LOGIC ; 5 z : OUT STD_LOGIC ) ; 6 END simple ; 7 ARCHITECTURE Behavior OF simple IS 8 TYPE State_type IS (A, B, C) ; 9 SIGNAL y : State_type ; 10 BEGIN 11 PROCESS ( Resetn, Clock ) 12 BEGIN 13 IF Resetn = '0' THEN 14 y <= A ; 15 ELSIF (Clock'EVENT AND Clock = '1') THEN 16 CASE y IS 17 WHEN A => 18 IF w = '0' THEN 19 y <= A ; 20 ELSE 21 y <= B ; 22 END IF ; 23 WHEN B => 24 IF w = '0' THEN 25 y <= A ; 26 ELSE 27 y <= C ; 28 END IF ; 29 WHEN C => 30 IF w = '0' THEN 31 y <= A ; 32 ELSE 33 y <= C ; 34 END IF ; 35 END CASE ; 36 END IF ; 37 END PROCESS ; 38 z <= '1' WHEN y = C ELSE '0' ; 39 END Behavior ; C z 1 = Reset B z 0 = A z 0 = w 0 = w 1 = w 1 = w 0 = w 0 = w 1 = NB output specified outside process block once state set State not visible, just output! Alternative styles in chapter 8 but KISS for ECE52
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
6 VHDL for Mealy-style FSM A w 0 = z 0 = w 1 = z 1 = B w 0 = z 0 = Reset w 1 = z 0 = LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mealy IS PORT ( Clock, Resetn, w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END mealy ; ARCHITECTURE Behavior OF mealy IS TYPE State_type IS (A, B) ; SIGNAL y : State_type ; BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; END CASE ; END IF ; END PROCESS ; PROCESS ( y, w ) BEGIN CASE y IS WHEN A => z <= '0' ; WHEN B => z <= w ; END CASE ; END PROCESS ; END Behavior ; Outputs and next states set in separate PROCESS
Background image of page 6
Image of page 7
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 28

Lecture 28 - ECE52 Spring 11 Lecture 28 3/25/11 Midterm 2...

This preview shows document pages 1 - 7. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online