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Lecture 36

# Lecture 36 - 1 ECE52 Spring 11 Lecture 36 1 page interim...

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Unformatted text preview: 1 ECE52 Spring 11 Lecture 36 4/13/11 1 page interim project progress report due Friday 2 Consider Mealy model of S-R latch • Non-obvious part is the don’t cares on the output – consider state A and input 10 (Set) – could argue output should be asserted immediately in Mealy model – but it will be asserted as soon as we get to stable state, so not asserting it on the unstable transition enhances our implementation flexibility – Judicious mapping lets Q=y, recovering original design when NOR gates used Present Next state Output, Q state SR = 00 01 10 11 00 01 10 11 A A A B A 0 0 0 B B A B A 1 1 (a) State table (b) State diagram 10/1 00/1 11/0 01/0 00/0 10/ – A B 01 – ∕ 11 – ∕ SR /Q – – – Present Next state Output, Q state SR = 00 01 10 11 00 01 10 11 A A A B A 0 0 0 B B A B A 1 1 (a) State table (b) State diagram 10/1 00/1 11/0 01/0 00/0 10/ – A B 01 – ∕ 11 – ∕ SR /Q – – – 3 Analysis example: Gated D latch • Just treat clock as one of the asynchronous inputs as we did in hazard analysis • analyzing, • appears redundant but Dy term needed to eliminate hazard. • Plug in combinations to generate tables D C Q Y y (a) Circuit Present Next state state CD = 00 01 10 11 y Y Y Y Y Q 0 0 0 0 1 0 1 1 1 0 1 1 (b) Excitation table Present Next state state CD = 00 01 10 11 Q A A A A B 0 B B B A B 1 (c) Flow table (d) State diagram x1 0x x0 0x 11 A 0 ∕ B 1 ∕ 10 CD D C Q Y y (a) Circuit Present Next state state CD = 00 01 10 11 y Y Y Y Y Q 0 0 0 0 1 0 1 1 1 0 1 1 (b) Excitation table Present Next state state CD = 00 01 10 11 Q A A A A B 0 B B B A B 1 (c) Flow table (d) State diagram x1 0x x0 0x 11 A 0 ∕ B 1 ∕ 10 CD Dy y C CD Y + + = 4 Analysis: Master/Slave D-FF • Yes it’s synchronous but also at some level all circuits are asynchronous – subject to asynch analysis and see what happens D Clk Q Q D C Q y s y m Master Slave Q D Clk Q Q From our latch analysis a few minutes ago (leaving out redundant term) s m s m m Cy y C Y y C CD Y + = + = 5...
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Lecture 36 - 1 ECE52 Spring 11 Lecture 36 1 page interim...

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